Add immediate operands and arithmetic operations to the x64 assembler.

src/x64/assembler-x64.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 45 matching lines @@
 // 3) By not using an enum, we are possibly preventing the compiler from
 // doing certain constant folds, which may significantly reduce the
 // code generated for some assembly instructions (because they boil down
 // to a few constants). If this is a problem, we could change the code
 // such that we use an enum in optimized mode, and the struct in debug
 // mode. This way we get the compile-time error checking in debug mode
 // and best performance in optimized code.
 //
 
 struct Register {
+  static Register toRegister(int code) {
+    Register r = {code};
+    return r;
+  }
   bool is_valid() const  { return 0 <= code_ && code_ < 16; }
   bool is(Register reg) const  { return code_ == reg.code_; }
   // The byte-register distinction of ai32 has dissapeared.
   bool is_byte_register() const  { return false; }
   int code() const  {
     ASSERT(is_valid());
     return code_;
   }
   int bit() const  {
     UNIMPLEMENTED();
@@ skipping 124 matching lines @@
       ? no_hint
       : ((hint == not_taken) ? taken : not_taken);
 }
 
 
 // -----------------------------------------------------------------------------
 // Machine instruction Immediates
 
 class Immediate BASE_EMBEDDED {
  public:
-  inline explicit Immediate(int64_t x);
-  inline explicit Immediate(const char* s);
-  inline explicit Immediate(const ExternalReference& ext);
-  inline explicit Immediate(Handle<Object> handle);
+  explicit Immediate(int32_t value) : value_(value) {}
   inline explicit Immediate(Smi* value);
 
-  static Immediate CodeRelativeOffset(Label* label) {
-    return Immediate(label);
-  }
-
-  bool is_zero() const { return x_ == 0 && rmode_ == RelocInfo::NONE; }
-  bool is_int8() const {
-    return -128 <= x_ && x_ < 128 && rmode_ == RelocInfo::NONE;
-  }
-  bool is_int16() const {
-    return -32768 <= x_ && x_ < 32768 && rmode_ == RelocInfo::NONE;
-  }
-  bool is_int32() const {
-    return V8_INT64_C(-2147483648) <= x_
-        && x_ < V8_INT64_C(2147483648)
-        && rmode_ == RelocInfo::NONE;
-  }
-
  private:
-  inline explicit Immediate(Label* value) { UNIMPLEMENTED(); }
-
-  int64_t x_;
-  RelocInfo::Mode rmode_;
+  int32_t value_;
 
   friend class Assembler;
 };
 
 
 // -----------------------------------------------------------------------------
 // Machine instruction Operands
 
 enum ScaleFactor {
   times_1 = 0,
@@ skipping 167 matching lines @@
   void push(const Operand& src);
   void push(Label* label, RelocInfo::Mode relocation_mode);
 
   void pop(Register dst);
   void pop(const Operand& dst);
 
   void enter(const Immediate& size);
   void leave();
 
   // Moves
-  void mov_b(Register dst, const Operand& src);
-  void mov_b(const Operand& dst, int8_t imm8);
-  void mov_b(const Operand& dst, Register src);
+  void movb(Register dst, const Operand& src);
+  void movb(const Operand& dst, int8_t imm8);
+  void movb(const Operand& dst, Register src);
 
-  void mov_w(Register dst, const Operand& src);
-  void mov_w(const Operand& dst, Register src);
+  void movq(Register dst, int32_t imm32);
+  void movq(Register dst, Immediate x);
+  void movq(Register dst, const Operand& src);
+  void movq(Register dst, Register src);
+  void movq(const Operand& dst, const Immediate& x);
+  void movq(const Operand& dst, Register src);
 
-  void mov(Register dst, int32_t imm32);
-  void mov(Register dst, const Immediate& x);
-  void mov(Register dst, Handle<Object> handle);
-  void mov(Register dst, const Operand& src);
-  void mov(Register dst, Register src);
-  void mov(const Operand& dst, const Immediate& x);
-  void mov(const Operand& dst, Handle<Object> handle);
-  void mov(const Operand& dst, Register src);
+  // New x64 instructions to load a 64-bit immediate into a register.
+  // All 64-bit immediates must have a relocation mode.
+  void movq(Register dst, void* ptr, RelocInfo::Mode rmode);
+  void movq(Register dst, int64_t value, RelocInfo::Mode rmode);
+  void movq(Register dst, const char* s, RelocInfo::Mode rmode);
+  void movq(Register dst, const ExternalReference& ext, RelocInfo::Mode rmode);
+  void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
+
+  // New x64 instruction to load from an immediate 64-bit pointer into RAX.
+  void load_rax(void* ptr, RelocInfo::Mode rmode);
 
   void movsx_b(Register dst, const Operand& src);
 
   void movsx_w(Register dst, const Operand& src);
 
   void movzx_b(Register dst, const Operand& src);
 
   void movzx_w(Register dst, const Operand& src);
 
   // Conditional moves
   void cmov(Condition cc, Register dst, int32_t imm32);
   void cmov(Condition cc, Register dst, Handle<Object> handle);
   void cmov(Condition cc, Register dst, const Operand& src);
 
   // Exchange two registers
   void xchg(Register dst, Register src);
 
   // Arithmetics
-  void adc(Register dst, int32_t imm32);
-  void adc(Register dst, const Operand& src);
+  void add(Register dst, Register src) {
+    arithmetic_op(0x03, dst, src);
+  }
 
-  void add(Register dst, Register src);
-  void add(Register dst, const Operand& src);
-  void add(const Operand& dst, const Immediate& x);
+  void add(Register dst, const Operand& src) {
+    arithmetic_op(0x03, dst, src);
+  }
+
+  void add(const Operand& dst, Register src) {
+    arithmetic_op(0x01, src, dst);
+  }
+
+  void add(Register dst, Immediate src) {
+    immediate_arithmetic_op(0x0, dst, src);
+  }
+
+  void add(const Operand& dst, Immediate src) {
+    immediate_arithmetic_op(0x0, dst, src);
+  }
+
+  void cmp(Register dst, Register src) {
+    arithmetic_op(0x3B, dst, src);
+  }
+
+  void cmp(Register dst, const Operand& src) {
+    arithmetic_op(0x3B, dst, src);
+  }
+
+  void cmp(const Operand& dst, Register src) {
+    arithmetic_op(0x39, src, dst);
+  }
+
+  void cmp(Register dst, Immediate src) {
+    immediate_arithmetic_op(0x7, dst, src);
+  }
+
+  void cmp(const Operand& dst, Immediate src) {
+    immediate_arithmetic_op(0x7, dst, src);
+  }
+
 
   void and_(Register dst, int32_t imm32);
   void and_(Register dst, const Operand& src);
   void and_(const Operand& src, Register dst);
   void and_(const Operand& dst, const Immediate& x);
 
   void cmpb(const Operand& op, int8_t imm8);
   void cmpb_al(const Operand& op);
   void cmpw_ax(const Operand& op);
   void cmpw(const Operand& op, Immediate imm16);
-  void cmp(Register reg, int32_t imm32);
-  void cmp(Register reg, Handle<Object> handle);
-  void cmp(Register reg, const Operand& op);
-  void cmp(const Operand& op, const Immediate& imm);
 
   void dec_b(Register dst);
 
   void dec(Register dst);
   void dec(const Operand& dst);
 
   void cdq();
 
   void idiv(Register src);
 
@@ skipping 221 matching lines @@
   byte byte_at(int pos)  { return buffer_[pos]; }
   uint32_t long_at(int pos)  {
     return *reinterpret_cast<uint32_t*>(addr_at(pos));
   }
   void long_at_put(int pos, uint32_t x)  {
     *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
   }
 
   // code emission
   void GrowBuffer();
-  inline void emit(uint32_t x);
+  inline void emitl(uint32_t x);
   inline void emit(Handle<Object> handle);
-  inline void emit(uint32_t x, RelocInfo::Mode rmode);
-  inline void emit(const Immediate& x);
-  inline void emit_w(const Immediate& x);
+  inline void emitq(uint64_t x, RelocInfo::Mode rmode);
+  void emit(Immediate x) { emitl(x.value_); }
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of both register codes.
+  // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
+  // REX.W is set.
   inline void emit_rex_64(Register reg, Register rm_reg);
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of the destination, index, and base register codes.
+  // The high bit of reg is used for REX.R, the high bit of op's base
+  // register is used for REX.B, and the high bit of op's index register
+  // is used for REX.X.  REX.W is set.
   inline void emit_rex_64(Register reg, const Operand& op);
 
   // Emit the code-object-relative offset of the label's position
   inline void emit_code_relative_offset(Label* label);
 
   // instruction generation
   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 
   // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
   // with a given destination expression and an immediate operand.  It attempts
   // to use the shortest encoding possible.
   // sel specifies the /n in the modrm byte (see the Intel PRM).
+  void arithmetic_op(byte opcode, Register dst, Register src);
+  void arithmetic_op(byte opcode, Register reg, const Operand& op);
+  void immediate_arithmetic_op(byte subcode, Register dst, Immediate src);
+  void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src);
+
   void emit_arith(int sel, Operand dst, const Immediate& x);
 
   void emit_operand(Register reg, const Operand& adr);
 
   void emit_farith(int b1, int b2, int i);
 
   // labels
   void print(Label* L);
   void bind_to(Label* L, int pos);
   void link_to(Label* L, Label* appendix);
 
   // record reloc info for current pc_
-  void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
+  void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0) {
+    UNIMPLEMENTED();
+  }
 
   friend class CodePatcher;
   friend class EnsureSpace;
 
   // Code buffer:
   // The buffer into which code and relocation info are generated.
   byte* buffer_;
   int buffer_size_;
   // True if the assembler owns the buffer, false if buffer is external.
   bool own_buffer_;
@@ skipping 38 matching lines @@
  private:
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_X64_ASSEMBLER_X64_H_