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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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141 *call_object_address() = target; | 141 *call_object_address() = target; |
142 } | 142 } |
143 | 143 |
144 | 144 |
145 Object** RelocInfo::call_object_address() { | 145 Object** RelocInfo::call_object_address() { |
146 UNIMPLEMENTED(); // IA32 code below. | 146 UNIMPLEMENTED(); // IA32 code below. |
147 ASSERT(IsCallInstruction()); | 147 ASSERT(IsCallInstruction()); |
148 return reinterpret_cast<Object**>(pc_ + 1); | 148 return reinterpret_cast<Object**>(pc_ + 1); |
149 } | 149 } |
150 | 150 |
| 151 |
| 152 void Operand::set_modrm(int mod, Register rm) { |
| 153 ASSERT((mod & -4) == 0); |
| 154 buf_[0] = mod << 6 | (rm.code() & 0x7); |
| 155 // Set REX.B to the high bit of rm.code(). |
| 156 rex_ |= (rm.code() >> 3); |
| 157 len_ = 1; |
| 158 } |
| 159 |
| 160 |
| 161 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { |
| 162 ASSERT(len_ == 1); |
| 163 ASSERT((scale & -4) == 0); |
| 164 // Use SIB with no index register only for base rsp or r12. |
| 165 ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12)); |
| 166 buf_[1] = scale << 6 | (index.code() & 0x7) << 3 | (base.code() & 0x7); |
| 167 rex_ |= (index.code() >> 3) << 1 | base.code() >> 3; |
| 168 len_ = 2; |
| 169 } |
| 170 |
| 171 |
| 172 void Operand::set_disp32(int32_t disp) { |
| 173 ASSERT(len_ == 1 || len_ == 2); |
| 174 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); |
| 175 *p = disp; |
| 176 len_ += sizeof(int32_t); |
| 177 } |
| 178 |
| 179 |
| 180 void Operand::set_dispr(intptr_t disp, RelocInfo::Mode rmode) { |
| 181 // This cannot be used in 64-bit mode. A 64-bit displacement |
| 182 // cannot be encoded, so relocatable 64-bit values must be |
| 183 // loaded as immediates. |
| 184 UNIMPLEMENTED(); |
| 185 } |
| 186 |
| 187 |
| 188 Operand::Operand(Register reg) { |
| 189 // reg |
| 190 set_modrm(3, reg); |
| 191 } |
| 192 |
151 } } // namespace v8::internal | 193 } } // namespace v8::internal |
152 | 194 |
153 #endif // V8_X64_ASSEMBLER_X64_INL_H_ | 195 #endif // V8_X64_ASSEMBLER_X64_INL_H_ |
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