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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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249 int32_t disp, | 249 int32_t disp, |
250 RelocInfo::Mode rmode) { | 250 RelocInfo::Mode rmode) { |
251 ASSERT(!index.is(esp)); // illegal addressing mode | 251 ASSERT(!index.is(esp)); // illegal addressing mode |
252 // [index*scale + disp/r] | 252 // [index*scale + disp/r] |
253 set_modrm(0, esp); | 253 set_modrm(0, esp); |
254 set_sib(scale, index, ebp); | 254 set_sib(scale, index, ebp); |
255 set_dispr(disp, rmode); | 255 set_dispr(disp, rmode); |
256 } | 256 } |
257 | 257 |
258 | 258 |
259 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { | |
260 ASSERT(len_ == 1); | |
261 ASSERT((scale & -4) == 0); | |
262 buf_[1] = scale << 6 | index.code() << 3 | base.code(); | |
263 len_ = 2; | |
264 } | |
265 | |
266 | |
267 void Operand::set_disp8(int8_t disp) { | |
268 ASSERT(len_ == 1 || len_ == 2); | |
269 *reinterpret_cast<int8_t*>(&buf_[len_++]) = disp; | |
270 } | |
271 | |
272 | |
273 bool Operand::is_reg(Register reg) const { | 259 bool Operand::is_reg(Register reg) const { |
274 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only. | 260 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only. |
275 && ((buf_[0] & 0x07) == reg.code()); // register codes match. | 261 && ((buf_[0] & 0x07) == reg.code()); // register codes match. |
276 } | 262 } |
277 | 263 |
278 // ----------------------------------------------------------------------------- | 264 // ----------------------------------------------------------------------------- |
279 // Implementation of Assembler | 265 // Implementation of Assembler |
280 | 266 |
281 // Emit a single byte. Must always be inlined. | 267 // Emit a single byte. Must always be inlined. |
282 #define EMIT(x) \ | 268 #define EMIT(x) \ |
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2231 push_insn[1] = 13; // Skip over coverage insns. | 2217 push_insn[1] = 13; // Skip over coverage insns. |
2232 if (coverage_log != NULL) { | 2218 if (coverage_log != NULL) { |
2233 fprintf(coverage_log, "%s\n", file_line); | 2219 fprintf(coverage_log, "%s\n", file_line); |
2234 fflush(coverage_log); | 2220 fflush(coverage_log); |
2235 } | 2221 } |
2236 } | 2222 } |
2237 | 2223 |
2238 #endif | 2224 #endif |
2239 | 2225 |
2240 } } // namespace v8::internal | 2226 } } // namespace v8::internal |
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