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Side by Side Diff: src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

Issue 11194045: Change BKPT and UDF encodings on ARM. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client
Patch Set: Fix one test that was using bkpt #0x6666. Created 8 years, 2 months ago
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1 /* 1 /*
2 * Copyright 2012 The Native Client Authors. All rights reserved. 2 * Copyright 2012 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can 3 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file. 4 * be found in the LICENSE file.
5 */ 5 */
6 6
7 // DO NOT EDIT: GENERATED CODE 7 // DO NOT EDIT: GENERATED CODE
8 8
9 #ifndef NACL_TRUSTED_BUT_NOT_TCB 9 #ifndef NACL_TRUSTED_BUT_NOT_TCB
10 #error This file is not meant for use in the TCB 10 #error This file is not meant for use in the TCB
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276 const NamedLoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694 LoadVectorRegisterL ist_Vpop_Rule_354_A1_A2_P694_instance_; 276 const NamedLoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694 LoadVectorRegisterL ist_Vpop_Rule_354_A1_A2_P694_instance_;
277 const NamedMaskedBinary2RegisterImmediateOp_BIC_immediate_A1 MaskedBinary2Regi sterImmediateOp_BIC_immediate_A1_instance_; 277 const NamedMaskedBinary2RegisterImmediateOp_BIC_immediate_A1 MaskedBinary2Regi sterImmediateOp_BIC_immediate_A1_instance_;
278 const NamedMaskedBinaryRegisterImmediateTest_TST_immediate_A1 MaskedBinaryRegi sterImmediateTest_TST_immediate_A1_instance_; 278 const NamedMaskedBinaryRegisterImmediateTest_TST_immediate_A1 MaskedBinaryRegi sterImmediateTest_TST_immediate_A1_instance_;
279 const NamedMoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1 MoveDoubleVfpRegisterOp_ Vmov_one_D_Rule_A1_instance_; 279 const NamedMoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1 MoveDoubleVfpRegisterOp_ Vmov_one_D_Rule_A1_instance_;
280 const NamedMoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1 MoveDoubleVfpRegisterOp_ Vmov_two_S_Rule_A1_instance_; 280 const NamedMoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1 MoveDoubleVfpRegisterOp_ Vmov_two_S_Rule_A1_instance_;
281 const NamedMoveImmediate12ToApsr_Msr_Rule_103_A1_P208 MoveImmediate12ToApsr_Ms r_Rule_103_A1_P208_instance_; 281 const NamedMoveImmediate12ToApsr_Msr_Rule_103_A1_P208 MoveImmediate12ToApsr_Ms r_Rule_103_A1_P208_instance_;
282 const NamedMoveVfpRegisterOp_Vmov_Rule_330_A1_P648 MoveVfpRegisterOp_Vmov_Rule _330_A1_P648_instance_; 282 const NamedMoveVfpRegisterOp_Vmov_Rule_330_A1_P648 MoveVfpRegisterOp_Vmov_Rule _330_A1_P648_instance_;
283 const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644 MoveVfpRegisterO pWithTypeSel_Vmov_Rule_328_A1_P644_instance_; 283 const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644 MoveVfpRegisterO pWithTypeSel_Vmov_Rule_328_A1_P644_instance_;
284 const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646 MoveVfpRegisterO pWithTypeSel_Vmov_Rule_329_A1_P646_instance_; 284 const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646 MoveVfpRegisterO pWithTypeSel_Vmov_Rule_329_A1_P646_instance_;
285 const NamedNotImplemented_None NotImplemented_None_instance_; 285 const NamedNotImplemented_None NotImplemented_None_instance_;
286 const NamedPermanentlyUndefined_Udf_Rule_A1 PermanentlyUndefined_Udf_Rule_A1_i nstance_;
286 const NamedPreloadRegisterImm12Op_Pld_Rule_117_A1_P236 PreloadRegisterImm12Op_ Pld_Rule_117_A1_P236_instance_; 287 const NamedPreloadRegisterImm12Op_Pld_Rule_117_A1_P236 PreloadRegisterImm12Op_ Pld_Rule_117_A1_P236_instance_;
287 const NamedPreloadRegisterImm12Op_Pld_Rule_118_A1_P238 PreloadRegisterImm12Op_ Pld_Rule_118_A1_P238_instance_; 288 const NamedPreloadRegisterImm12Op_Pld_Rule_118_A1_P238 PreloadRegisterImm12Op_ Pld_Rule_118_A1_P238_instance_;
288 const NamedPreloadRegisterImm12Op_Pldw_Rule_117_A1_P236 PreloadRegisterImm12Op _Pldw_Rule_117_A1_P236_instance_; 289 const NamedPreloadRegisterImm12Op_Pldw_Rule_117_A1_P236 PreloadRegisterImm12Op _Pldw_Rule_117_A1_P236_instance_;
289 const NamedPreloadRegisterImm12Op_Pli_Rule_120_A1_P242 PreloadRegisterImm12Op_ Pli_Rule_120_A1_P242_instance_; 290 const NamedPreloadRegisterImm12Op_Pli_Rule_120_A1_P242 PreloadRegisterImm12Op_ Pli_Rule_120_A1_P242_instance_;
290 const NamedPreloadRegisterPairOp_Pli_Rule_121_A1_P244 PreloadRegisterPairOp_Pl i_Rule_121_A1_P244_instance_; 291 const NamedPreloadRegisterPairOp_Pli_Rule_121_A1_P244 PreloadRegisterPairOp_Pl i_Rule_121_A1_P244_instance_;
291 const NamedPreloadRegisterPairOpWAndRnNotPc_Pld_Rule_119_A1_P240 PreloadRegist erPairOpWAndRnNotPc_Pld_Rule_119_A1_P240_instance_; 292 const NamedPreloadRegisterPairOpWAndRnNotPc_Pld_Rule_119_A1_P240 PreloadRegist erPairOpWAndRnNotPc_Pld_Rule_119_A1_P240_instance_;
292 const NamedPreloadRegisterPairOpWAndRnNotPc_Pldw_Rule_119_A1_P240 PreloadRegis terPairOpWAndRnNotPc_Pldw_Rule_119_A1_P240_instance_; 293 const NamedPreloadRegisterPairOpWAndRnNotPc_Pldw_Rule_119_A1_P240 PreloadRegis terPairOpWAndRnNotPc_Pldw_Rule_119_A1_P240_instance_;
293 const NamedRoadblock_Udf_Rule_A1 Roadblock_Udf_Rule_A1_instance_;
294 const NamedStore2RegisterImm12Op_Str_Rule_194_A1_P384 Store2RegisterImm12Op_St r_Rule_194_A1_P384_instance_; 294 const NamedStore2RegisterImm12Op_Str_Rule_194_A1_P384 Store2RegisterImm12Op_St r_Rule_194_A1_P384_instance_;
295 const NamedStore2RegisterImm12Op_Strb_Rule_197_A1_P390 Store2RegisterImm12Op_S trb_Rule_197_A1_P390_instance_; 295 const NamedStore2RegisterImm12Op_Strb_Rule_197_A1_P390 Store2RegisterImm12Op_S trb_Rule_197_A1_P390_instance_;
296 const NamedStore2RegisterImm12OpRnNotRtOnWriteback_Push_Rule_123_A2_P248 Store 2RegisterImm12OpRnNotRtOnWriteback_Push_Rule_123_A2_P248_instance_; 296 const NamedStore2RegisterImm12OpRnNotRtOnWriteback_Push_Rule_123_A2_P248 Store 2RegisterImm12OpRnNotRtOnWriteback_Push_Rule_123_A2_P248_instance_;
297 const NamedStore2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImm8 DoubleOp_Strd_Rule_200_A1_P396_instance_; 297 const NamedStore2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImm8 DoubleOp_Strd_Rule_200_A1_P396_instance_;
298 const NamedStore2RegisterImm8Op_Strh_Rule_207_A1_P410 Store2RegisterImm8Op_Str h_Rule_207_A1_P410_instance_; 298 const NamedStore2RegisterImm8Op_Strh_Rule_207_A1_P410 Store2RegisterImm8Op_Str h_Rule_207_A1_P410_instance_;
299 const NamedStore3RegisterDoubleOp_Strd_Rule_201_A1_P398 Store3RegisterDoubleOp _Strd_Rule_201_A1_P398_instance_; 299 const NamedStore3RegisterDoubleOp_Strd_Rule_201_A1_P398 Store3RegisterDoubleOp _Strd_Rule_201_A1_P398_instance_;
300 const NamedStore3RegisterImm5Op_Str_Rule_195_A1_P386 Store3RegisterImm5Op_Str_ Rule_195_A1_P386_instance_; 300 const NamedStore3RegisterImm5Op_Str_Rule_195_A1_P386 Store3RegisterImm5Op_Str_ Rule_195_A1_P386_instance_;
301 const NamedStore3RegisterImm5Op_Strb_Rule_198_A1_P392 Store3RegisterImm5Op_Str b_Rule_198_A1_P392_instance_; 301 const NamedStore3RegisterImm5Op_Strb_Rule_198_A1_P392 Store3RegisterImm5Op_Str b_Rule_198_A1_P392_instance_;
302 const NamedStore3RegisterOp_Strh_Rule_208_A1_P412 Store3RegisterOp_Strh_Rule_2 08_A1_P412_instance_; 302 const NamedStore3RegisterOp_Strh_Rule_208_A1_P412 Store3RegisterOp_Strh_Rule_2 08_A1_P412_instance_;
303 const NamedStoreExclusive3RegisterDoubleOp_Strexd_Rule_204_A1_P404 StoreExclus ive3RegisterDoubleOp_Strexd_Rule_204_A1_P404_instance_; 303 const NamedStoreExclusive3RegisterDoubleOp_Strexd_Rule_204_A1_P404 StoreExclus ive3RegisterDoubleOp_Strexd_Rule_204_A1_P404_instance_;
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777 const nacl_arm_dec::Instruction inst) const; 777 const nacl_arm_dec::Instruction inst) const;
778 inline const NamedClassDecoder& decode_unconditional_instructions( 778 inline const NamedClassDecoder& decode_unconditional_instructions(
779 const nacl_arm_dec::Instruction inst) const; 779 const nacl_arm_dec::Instruction inst) const;
780 // Defines default action if parse tables don't define what action 780 // Defines default action if parse tables don't define what action
781 // to take. 781 // to take.
782 const NotImplementedNamed not_implemented_; 782 const NotImplementedNamed not_implemented_;
783 }; 783 };
784 784
785 } // namespace nacl_arm_test 785 } // namespace nacl_arm_test
786 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_NAMED_DECODE R_H_ 786 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_NAMED_DECODE R_H_
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