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| 1 /* | 1 /* |
| 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. | 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. |
| 3 * Use of this source code is governed by a BSD-style license that can be | 3 * Use of this source code is governed by a BSD-style license that can be |
| 4 * found in the LICENSE file. | 4 * found in the LICENSE file. |
| 5 */ | 5 */ |
| 6 | 6 |
| 7 /* |
| 8 * Hand-written Ragel machines and actions used in validator and decoding. |
| 9 * |
| 10 * Note: this file includes many different machines which are supposed to be |
| 11 * used together to implement decoding. |
| 12 * |
| 13 * E.g. modrm_parsing_ia32 implements “ModR/M style memory access” used in ia32 |
| 14 * mode, but actions it uses may come from modrm_actions_ia32 or, alternatively, |
| 15 * the higher-level machine may have it's own unique implementation of actions. |
| 16 */ |
| 17 |
| 7 %%{ | 18 %%{ |
| 8 machine prefix_actions; | 19 machine prefix_actions; |
| 9 | 20 |
| 10 action branch_not_taken { | 21 action branch_not_taken { |
| 11 SET_BRANCH_NOT_TAKEN(TRUE); | 22 SET_BRANCH_NOT_TAKEN(TRUE); |
| 12 } | 23 } |
| 13 action branch_taken { | 24 action branch_taken { |
| 14 SET_BRANCH_TAKEN(TRUE); | 25 SET_BRANCH_TAKEN(TRUE); |
| 15 } | 26 } |
| 16 action data16_prefix { | 27 action data16_prefix { |
| (...skipping 894 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 911 action rel8_operand_end { } | 922 action rel8_operand_end { } |
| 912 action rel16_operand_begin { } | 923 action rel16_operand_begin { } |
| 913 action rel16_operand_end { } | 924 action rel16_operand_end { } |
| 914 action rel32_operand_begin { } | 925 action rel32_operand_begin { } |
| 915 action rel32_operand_end { } | 926 action rel32_operand_end { } |
| 916 | 927 |
| 917 rel8 = any >rel8_operand_begin @rel8_operand_end; | 928 rel8 = any >rel8_operand_begin @rel8_operand_end; |
| 918 rel16 = any{2} @~rel16_operand_begin @rel16_operand_end; | 929 rel16 = any{2} @~rel16_operand_begin @rel16_operand_end; |
| 919 rel32 = any{4} @~rel32_operand_begin @rel32_operand_end; | 930 rel32 = any{4} @~rel32_operand_begin @rel32_operand_end; |
| 920 }%% | 931 }%% |
| 932 |
| 933 %%{ |
| 934 machine decoder; |
| 935 |
| 936 decoder = (one_instruction |
| 937 @{ |
| 938 process_instruction(instruction_start, current_position+1, &instruction, |
| 939 userdata); |
| 940 instruction_start = current_position + 1; |
| 941 SET_DISP_TYPE(DISPNONE); |
| 942 SET_IMM_TYPE(IMMNONE); |
| 943 SET_IMM2_TYPE(IMMNONE); |
| 944 SET_REX_PREFIX(FALSE); |
| 945 SET_DATA16_PREFIX(FALSE); |
| 946 SET_LOCK_PREFIX(FALSE); |
| 947 SET_REPNZ_PREFIX(FALSE); |
| 948 SET_REPZ_PREFIX(FALSE); |
| 949 SET_BRANCH_NOT_TAKEN(FALSE); |
| 950 SET_BRANCH_TAKEN(FALSE); |
| 951 /* Top three bis of VEX2 are inverted: see AMD/Intel manual. */ |
| 952 SET_VEX_PREFIX2(0xe0); |
| 953 SET_VEX_PREFIX3(0x00); |
| 954 SET_ATT_INSTRUCTION_SUFFIX(NULL); |
| 955 CLEAR_SPURIOUS_DATA16(); |
| 956 CLEAR_SPURIOUS_REX_B(); |
| 957 CLEAR_SPURIOUS_REX_X(); |
| 958 CLEAR_SPURIOUS_REX_R(); |
| 959 CLEAR_SPURIOUS_REX_W(); |
| 960 })* |
| 961 $!{ process_error(current_position, userdata); |
| 962 result = FALSE; |
| 963 goto error_detected; |
| 964 }; |
| 965 }%% |
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