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Issue 11000033: Move validator_x86_XX.rl out of unreviewed. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 2 months ago
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« src/trusted/validator_ragel/unreviewed/decoder_test.c ('K') | « src/trusted/validator_ragel/unreviewed/decoder_test.c ('k') | src/trusted/validator_ragel/unreviewed/decoder_x86_64.rl » ('j') | src/trusted/validator_ragel/validator_internal.h » ('J')
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1 /*
2 * Copyright (c) 2011 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #include <assert.h>
8 #include <stddef.h>
9 #include <stdio.h>
10 #include <stdlib.h>
11 #include <string.h>
12
13 #include "native_client/src/shared/utils/types.h"
14 #include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h"
15
16 #include "native_client/src/trusted/validator_ragel/gen/decoder_x86_32_instructi on_consts.h"
17
18 %%{
19 machine x86_32_decoder;
20 alphtype unsigned char;
21 variable p current_position;
22 variable pe end_of_data;
23 variable eof end_of_data;
24 variable cs current_state;
25
26 include byte_machine "byte_machines.rl";
27
28 include prefix_actions
29 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
30 include prefixes_parsing
31 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
32 include vex_actions_ia32
33 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
34 include vex_parsing_ia32
35 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
36 include att_suffix_actions
37 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
38 include set_spurious_prefixes
39 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
40 include displacement_fields_actions
41 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
42 include displacement_fields_parsing
43 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
44 include modrm_actions_ia32
45 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
46 include modrm_parsing_ia32
47 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
48 include operand_actions_ia32
49 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
50 include immediate_fields_actions
51 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
52 include immediate_fields_parsing_ia32
53 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
54 include relative_fields_actions
55 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
56 include relative_fields_parsing
57 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
58 include cpuid_actions
59 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
60
61 include decode_x86_32 "decoder_x86_32_instruction.rl";
62
63 main := (one_instruction
64 @{
65 switch (instruction.rm.disp_type) {
66 case DISPNONE: instruction.rm.offset = 0; break;
67 case DISP8: instruction.rm.offset = (int8_t) *disp; break;
68 case DISP16: instruction.rm.offset =
69 (int16_t) (disp[0] + 256U * disp[1]);
70 break;
71 case DISP32: instruction.rm.offset = (int32_t)
72 (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3]))));
73 break;
74 case DISP64: assert(FALSE);
75 }
76 switch (imm_operand) {
77 case IMMNONE: instruction.imm[0] = 0; break;
78 case IMM2: instruction.imm[0] = imm[0] & 0x03; break;
79 case IMM8: instruction.imm[0] = imm[0]; break;
80 case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1]));
81 break;
82 case IMM32: instruction.imm[0] = (uint64_t)
83 (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3]))));
84 break;
85 }
86 switch (imm2_operand) {
87 case IMMNONE: instruction.imm[1] = 0; break;
88 case IMM2: instruction.imm[1] = imm2[0] & 0x03; break;
89 case IMM8: instruction.imm[1] = imm2[0]; break;
90 case IMM16: instruction.imm[1] = (uint64_t)
91 (imm2[0] + 256U * (imm2[1]));
92 break;
93 case IMM32: instruction.imm[1] = (uint64_t)
94 (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3]))));
95 break;
96 }
97 process_instruction(instruction_start, current_position+1, &instruction,
98 userdata);
99 instruction_start = current_position + 1;
100 SET_DISP_TYPE(DISPNONE);
101 SET_IMM_TYPE(IMMNONE);
102 SET_IMM2_TYPE(IMMNONE);
103 SET_DATA16_PREFIX(FALSE);
104 SET_LOCK_PREFIX(FALSE);
105 SET_REPNZ_PREFIX(FALSE);
106 SET_REPZ_PREFIX(FALSE);
107 SET_BRANCH_NOT_TAKEN(FALSE);
108 SET_BRANCH_TAKEN(FALSE);
109 SET_VEX_PREFIX3(0x00);
110 SET_ATT_INSTRUCTION_SUFFIX(NULL);
111 })*
112 $!{ process_error(current_position, userdata);
113 result = FALSE;
114 goto error_detected;
115 };
116
117 }%%
118
119 %% write data;
120
121 #define GET_VEX_PREFIX3() vex_prefix3
122 #define SET_VEX_PREFIX3(P) vex_prefix3 = (P)
123 #define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S)
124 #define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S)
125 #define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S)
126 #define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S)
127 #define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S)
128 #define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S)
129 #define SET_INSTRUCTION_NAME(N) instruction.name = (N)
130 #define GET_OPERAND_NAME(N) instruction.operands[(N)].name
131 #define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S)
132 #define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S)
133 #define SET_OPERANDS_COUNT(N) instruction.operands_count = (N)
134 #define SET_MODRM_BASE(N) instruction.rm.base = (N)
135 #define SET_MODRM_INDEX(N) instruction.rm.index = (N)
136 #define SET_MODRM_SCALE(S) instruction.rm.scale = (S)
137 #define SET_DISP_TYPE(T) instruction.rm.disp_type = (T)
138 #define SET_DISP_PTR(P) disp = (P)
139 #define SET_IMM_TYPE(T) imm_operand = (T)
140 #define SET_IMM_PTR(P) imm = (P)
141 #define SET_IMM2_TYPE(T) imm2_operand = (T)
142 #define SET_IMM2_PTR(P) imm2 = (P)
143 #define SET_CPU_FEATURE(F)
144 #define SET_ATT_INSTRUCTION_SUFFIX(S) instruction.att_instruction_suffix = (S)
145
146 enum {
147 REX_B = 1,
148 REX_X = 2,
149 REX_R = 4,
150 REX_W = 8
151 };
152
153 enum imm_mode {
154 IMMNONE,
155 IMM2,
156 IMM8,
157 IMM16,
158 IMM32
159 };
160
161 int DecodeChunkIA32(const uint8_t *data, size_t size,
162 ProcessInstructionFunc process_instruction,
163 ProcessDecodingErrorFunc process_error, void *userdata) {
164 const uint8_t *current_position = data;
165 const uint8_t *end_of_data = data + size;
166 const uint8_t *disp = NULL;
167 const uint8_t *imm = NULL;
168 const uint8_t *imm2 = NULL;
169 const uint8_t *instruction_start = current_position;
170 uint8_t vex_prefix3 = 0x00;
171 enum imm_mode imm_operand = IMMNONE;
172 enum imm_mode imm2_operand = IMMNONE;
173 struct Instruction instruction;
174 int result = TRUE;
175
176 int current_state;
177
178 /* Not used in ia32_mode. */
179 instruction.prefix.rex = 0;
180
181 SET_DISP_TYPE(DISPNONE);
182 SET_IMM_TYPE(IMMNONE);
183 SET_IMM2_TYPE(IMMNONE);
184 SET_DATA16_PREFIX(FALSE);
185 SET_LOCK_PREFIX(FALSE);
186 SET_REPNZ_PREFIX(FALSE);
187 SET_REPZ_PREFIX(FALSE);
188 SET_BRANCH_NOT_TAKEN(FALSE);
189 SET_BRANCH_TAKEN(FALSE);
190 SET_ATT_INSTRUCTION_SUFFIX(NULL);
191 instruction.prefix.data16_spurious = FALSE;
192 instruction.prefix.rex_b_spurious = FALSE;
193 instruction.prefix.rex_x_spurious = FALSE;
194 instruction.prefix.rex_r_spurious = FALSE;
195 instruction.prefix.rex_w_spurious = FALSE;
196
197 %% write init;
198 %% write exec;
199
200 error_detected:
201 return result;
202 }
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« src/trusted/validator_ragel/unreviewed/decoder_test.c ('K') | « src/trusted/validator_ragel/unreviewed/decoder_test.c ('k') | src/trusted/validator_ragel/unreviewed/decoder_x86_64.rl » ('j') | src/trusted/validator_ragel/validator_internal.h » ('J')

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