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1 /* | 1 /* |
2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. | 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. |
3 * Use of this source code is governed by a BSD-style license that can be | 3 * Use of this source code is governed by a BSD-style license that can be |
4 * found in the LICENSE file. | 4 * found in the LICENSE file. |
5 */ | 5 */ |
6 | 6 |
7 #include <assert.h> | 7 #include <assert.h> |
8 #include <stddef.h> | 8 #include <stddef.h> |
9 #include <stdio.h> | 9 #include <stdio.h> |
10 #include <stdlib.h> | 10 #include <stdlib.h> |
11 #include <string.h> | 11 #include <string.h> |
12 | 12 |
13 #include "native_client/src/shared/utils/types.h" | 13 #include "native_client/src/shared/utils/types.h" |
14 #include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h" | 14 #include "native_client/src/trusted/validator_ragel/decoder_internal.h" |
15 | 15 |
16 #include "native_client/src/trusted/validator_ragel/gen/decoder_x86_32_instructi on_consts.h" | 16 #include "native_client/src/trusted/validator_ragel/gen/decoder_x86_32_instructi on_consts.h" |
17 | 17 |
18 #define GET_REX_PREFIX() | |
Brad Chen
2012/10/04 17:26:04
These are weird-looking defines. A comment would b
khim
2012/10/05 08:22:53
Removed: they are no longer used in 32-bit mode at
| |
19 #define SET_REX_PREFIX(P) | |
20 #define GET_VEX_PREFIX2() | |
21 #define SET_VEX_PREFIX2(P) | |
22 | |
18 %%{ | 23 %%{ |
19 machine x86_32_decoder; | 24 machine x86_32_decoder; |
20 alphtype unsigned char; | 25 alphtype unsigned char; |
21 variable p current_position; | 26 variable p current_position; |
22 variable pe end_of_data; | 27 variable pe end_of_data; |
23 variable eof end_of_data; | 28 variable eof end_of_data; |
24 variable cs current_state; | 29 variable cs current_state; |
25 | 30 |
26 include byte_machine "byte_machines.rl"; | 31 include byte_machine "byte_machines.rl"; |
27 | 32 |
(...skipping 21 matching lines...) Expand all Loading... | |
49 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | 54 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; |
50 include relative_fields_actions | 55 include relative_fields_actions |
51 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | 56 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; |
52 include relative_fields_parsing | 57 include relative_fields_parsing |
53 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | 58 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; |
54 include cpuid_actions | 59 include cpuid_actions |
55 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | 60 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; |
56 | 61 |
57 include decode_x86_32 "decoder_x86_32_instruction.rl"; | 62 include decode_x86_32 "decoder_x86_32_instruction.rl"; |
58 | 63 |
59 main := (one_instruction | 64 include decoder |
60 @{ | 65 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; |
61 switch (instruction.rm.disp_type) { | |
62 case DISPNONE: instruction.rm.offset = 0; break; | |
63 case DISP8: instruction.rm.offset = (int8_t) *disp; break; | |
64 case DISP16: instruction.rm.offset = | |
65 (int16_t) (disp[0] + 256U * disp[1]); | |
66 break; | |
67 case DISP32: instruction.rm.offset = (int32_t) | |
68 (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3])))); | |
69 break; | |
70 case DISP64: assert(FALSE); | |
71 } | |
72 switch (imm_operand) { | |
73 case IMMNONE: instruction.imm[0] = 0; break; | |
74 case IMM2: instruction.imm[0] = imm[0] & 0x03; break; | |
75 case IMM8: instruction.imm[0] = imm[0]; break; | |
76 case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1])); | |
77 break; | |
78 case IMM32: instruction.imm[0] = (uint64_t) | |
79 (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3])))); | |
80 break; | |
81 } | |
82 switch (imm2_operand) { | |
83 case IMMNONE: instruction.imm[1] = 0; break; | |
84 case IMM2: instruction.imm[1] = imm2[0] & 0x03; break; | |
85 case IMM8: instruction.imm[1] = imm2[0]; break; | |
86 case IMM16: instruction.imm[1] = (uint64_t) | |
87 (imm2[0] + 256U * (imm2[1])); | |
88 break; | |
89 case IMM32: instruction.imm[1] = (uint64_t) | |
90 (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3])))); | |
91 break; | |
92 } | |
93 process_instruction(instruction_start, current_position+1, &instruction, | |
94 userdata); | |
95 instruction_start = current_position + 1; | |
96 SET_DISP_TYPE(DISPNONE); | |
97 SET_IMM_TYPE(IMMNONE); | |
98 SET_IMM2_TYPE(IMMNONE); | |
99 SET_DATA16_PREFIX(FALSE); | |
100 SET_LOCK_PREFIX(FALSE); | |
101 SET_REPNZ_PREFIX(FALSE); | |
102 SET_REPZ_PREFIX(FALSE); | |
103 SET_BRANCH_NOT_TAKEN(FALSE); | |
104 SET_BRANCH_TAKEN(FALSE); | |
105 SET_VEX_PREFIX3(0x00); | |
106 })* | |
107 $!{ process_error(current_position, userdata); | |
108 result = FALSE; | |
109 goto error_detected; | |
110 }; | |
111 | 66 |
67 main := decoder; | |
112 }%% | 68 }%% |
113 | 69 |
114 %% write data; | 70 %% write data; |
115 | 71 |
116 #define GET_VEX_PREFIX3() vex_prefix3 | |
117 #define SET_VEX_PREFIX3(P) vex_prefix3 = (P) | |
118 #define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S) | |
119 #define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S) | |
120 #define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S) | |
121 #define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S) | |
122 #define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S) | |
123 #define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S) | |
124 #define SET_INSTRUCTION_NAME(N) instruction.name = (N) | |
125 #define GET_OPERAND_NAME(N) instruction.operands[(N)].name | |
126 #define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S) | |
127 #define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S) | |
128 #define SET_OPERANDS_COUNT(N) instruction.operands_count = (N) | |
129 #define SET_MODRM_BASE(N) instruction.rm.base = (N) | |
130 #define SET_MODRM_INDEX(N) instruction.rm.index = (N) | |
131 #define SET_MODRM_SCALE(S) instruction.rm.scale = (S) | |
132 #define SET_DISP_TYPE(T) instruction.rm.disp_type = (T) | |
133 #define SET_DISP_PTR(P) disp = (P) | |
134 #define SET_IMM_TYPE(T) imm_operand = (T) | |
135 #define SET_IMM_PTR(P) imm = (P) | |
136 #define SET_IMM2_TYPE(T) imm2_operand = (T) | |
137 #define SET_IMM2_PTR(P) imm2 = (P) | |
138 #define SET_CPU_FEATURE(F) | |
139 | |
140 enum { | |
141 REX_B = 1, | |
142 REX_X = 2, | |
143 REX_R = 4, | |
144 REX_W = 8 | |
145 }; | |
146 | |
147 enum imm_mode { | |
148 IMMNONE, | |
149 IMM2, | |
150 IMM8, | |
151 IMM16, | |
152 IMM32 | |
153 }; | |
154 | |
155 int DecodeChunkIA32(const uint8_t *data, size_t size, | 72 int DecodeChunkIA32(const uint8_t *data, size_t size, |
156 process_instruction_func process_instruction, | 73 ProcessInstructionFunc process_instruction, |
157 process_decoding_error_func process_error, void *userdata) { | 74 ProcessDecodingErrorFunc process_error, void *userdata) { |
158 const uint8_t *current_position = data; | 75 const uint8_t *current_position = data; |
159 const uint8_t *end_of_data = data + size; | 76 const uint8_t *end_of_data = data + size; |
160 const uint8_t *disp = NULL; | |
161 const uint8_t *imm = NULL; | |
162 const uint8_t *imm2 = NULL; | |
163 const uint8_t *instruction_start = current_position; | 77 const uint8_t *instruction_start = current_position; |
164 uint8_t vex_prefix3 = 0x00; | 78 uint8_t vex_prefix3 = 0x00; |
165 enum imm_mode imm_operand = IMMNONE; | 79 enum ImmediateMode imm_operand = IMMNONE; |
166 enum imm_mode imm2_operand = IMMNONE; | 80 enum ImmediateMode imm2_operand = IMMNONE; |
167 struct instruction instruction; | 81 struct Instruction instruction; |
168 int result = TRUE; | 82 int result = TRUE; |
169 | 83 |
170 int current_state; | 84 int current_state; |
171 | 85 |
172 /* Not used in ia32_mode. */ | 86 /* Not used in ia32_mode. */ |
173 instruction.prefix.rex = 0; | 87 instruction.prefix.rex = 0; |
174 | 88 |
175 SET_DISP_TYPE(DISPNONE); | 89 SET_DISP_TYPE(DISPNONE); |
176 SET_IMM_TYPE(IMMNONE); | 90 SET_IMM_TYPE(IMMNONE); |
177 SET_IMM2_TYPE(IMMNONE); | 91 SET_IMM2_TYPE(IMMNONE); |
178 SET_DATA16_PREFIX(FALSE); | 92 SET_DATA16_PREFIX(FALSE); |
179 SET_LOCK_PREFIX(FALSE); | 93 SET_LOCK_PREFIX(FALSE); |
180 SET_REPNZ_PREFIX(FALSE); | 94 SET_REPNZ_PREFIX(FALSE); |
181 SET_REPZ_PREFIX(FALSE); | 95 SET_REPZ_PREFIX(FALSE); |
182 SET_BRANCH_NOT_TAKEN(FALSE); | 96 SET_BRANCH_NOT_TAKEN(FALSE); |
183 SET_BRANCH_TAKEN(FALSE); | 97 SET_BRANCH_TAKEN(FALSE); |
184 | 98 |
185 %% write init; | 99 %% write init; |
186 %% write exec; | 100 %% write exec; |
187 | 101 |
188 error_detected: | 102 error_detected: |
189 return result; | 103 return result; |
190 } | 104 } |
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