Move validator_x86_XX.rl out of unreviewed.

src/trusted/validator_ragel/unreviewed/decoder_internal.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * This file contains common parts of x86-32 and x86-64 internals (inline
  * functions and defines).
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODER_INTERNAL_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODER_INTERNAL_H_
 
-#include "native_client/src/trusted/validator_ragel/unreviewed/decoder.h"
+#define GET_REX_PREFIX() instruction.prefix.rex
+#define SET_REX_PREFIX(P) instruction.prefix.rex = (P)
+#define GET_VEX_PREFIX2() vex_prefix2
+#define SET_VEX_PREFIX2(P) vex_prefix2 = (P)
+#define GET_VEX_PREFIX3() vex_prefix3
+#define SET_VEX_PREFIX3(P) vex_prefix3 = (P)
+#define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S)
+#define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S)
+#define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S)
+#define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S)
+#define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S)
+#define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S)
+#define SET_INSTRUCTION_NAME(N) instruction.name = (N)
+#define GET_OPERAND_NAME(N) instruction.operands[(N)].name
+#define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S)
+#define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S)
+#define SET_OPERANDS_COUNT(N) instruction.operands_count = (N)
+#define SET_MODRM_BASE(N) instruction.rm.base = (N)
+#define SET_MODRM_INDEX(N) instruction.rm.index = (N)
+#define SET_MODRM_SCALE(S) instruction.rm.scale = (S)
+#define SET_DISP_TYPE(T) instruction.rm.disp_type = (T)
+#define SET_DISP_PTR(P)                                                        \
+  switch (instruction.rm.disp_type) {                                          \
+    case DISPNONE:                                                             \
+      instruction.rm.offset = 0;                                               \
+      break;                                                                   \
+    case DISP8:                                                                \
+      instruction.rm.offset = AnyFieldValue8bitSigned(P);                      \
+    case DISP16:                                                               \
+      instruction.rm.offset = AnyFieldValue16bitSigned(P);                     \
+      break;                                                                   \
+    case DISP32:                                                               \
+      instruction.rm.offset = AnyFieldValue32bitSigned(P);                     \
+      break;                                                                   \
+    case DISP64:                                                               \
+      instruction.rm.offset = AnyFieldValue64bitSigned(P);                     \
+      break;                                                                   \
+  }
+#define SET_IMM_TYPE(T) imm_operand = (T)
+#define SET_IMM_PTR(P) SET_IMM_PTR(P, 0, imm2_operand)
+#define SET_IMM2_TYPE(T) imm2_operand = (T)
+#define SET_IMM2_PTR(P) SET_IMM_PTR(P, 1, imm2_operand)
+#define SET_IMM_PTR(P, N, O)                                                   \
+  switch (O) {                                                                 \
+    case IMMNONE:                                                              \
+      instruction.imm[N] = 0;                                                  \
+      break;                                                                   \
+    case IMM2:                                                                 \
+      instruction.imm[N] = P[0] & 0x03;                                        \
+      break;                                                                   \
+    case IMM8:                                                                 \
+      instruction.imm[N] = AnyFieldValue8bitUnsigned(P);                       \
+      break;                                                                   \
+    case IMM16:                                                                \
+      instruction.imm[N] = AnyFieldValue16bitUnsigned(P);                      \
+      break;                                                                   \
+    case IMM32:                                                                \
+      instruction.imm[N] = AnyFieldValue32bitUnsigned(P);                      \
+      break;                                                                   \
+    case IMM64:                                                                \
+      instruction.imm[N] = AnyFieldValue64bitUnsigned(P);                      \
+      break;                                                                   \
+  }
+#define SET_CPU_FEATURE(F)
 
-#if NACL_WINDOWS
-# define FORCEINLINE __forceinline
-#else
-# define FORCEINLINE __inline __attribute__ ((always_inline))
-#endif
+enum {
+  REX_B = 1,
+  REX_X = 2,
+  REX_R = 4,
+  REX_W = 8
+};
 
-static FORCEINLINE uint8_t RegFromOpcode(uint8_t modrm) {
-  return modrm & 0x07;
-}
-
-static FORCEINLINE uint8_t ModFromModRM(uint8_t modrm) {
-  return modrm >> 6;
-}
-
-static FORCEINLINE uint8_t RegFromModRM(uint8_t modrm) {
-  return (modrm & 0x38) >> 3;
-}
-
-static FORCEINLINE uint8_t RMFromModRM(uint8_t modrm) {
-  return modrm & 0x07;
-}
-
-static FORCEINLINE uint8_t ScaleFromSIB(uint8_t sib) {
-  return sib >> 6;
-}
-
-static FORCEINLINE uint8_t IndexFromSIB(uint8_t sib) {
-  return (sib & 0x38) >> 3;
-}
-
-static FORCEINLINE uint8_t BaseFromSIB(uint8_t sib) {
-  return sib & 0x07;
-}
-
-static FORCEINLINE uint8_t BaseExtentionFromREX(uint8_t rex) {
-  return (rex & 0x01) << 3;
-}
-
-static FORCEINLINE uint8_t BaseExtentionFromVEX(uint8_t vex2) {
-  return ((~vex2) & 0x20) >> 2;
-}
-
-static FORCEINLINE uint8_t IndexExtentionFromREX(uint8_t rex) {
-  return (rex & 0x02) << 2;
-}
-
-static FORCEINLINE uint8_t IndexExtentionFromVEX(uint8_t vex2) {
-  return ((~vex2) & 0x40) >> 3;
-}
-
-static FORCEINLINE uint8_t RegisterExtentionFromREX(uint8_t rex) {
-  return (rex & 0x04) << 1;
-}
-
-static FORCEINLINE uint8_t RegisterExtentionFromVEX(uint8_t vex2) {
-  return ((~vex2) & 0x80) >> 4;
-}
-
-static FORCEINLINE uint8_t GetOperandFromVexIA32(uint8_t vex3) {
-  return ((~vex3) & 0x38) >> 3;
-}
-
-static FORCEINLINE uint8_t GetOperandFromVexAMD64(uint8_t vex3) {
-  return ((~vex3) & 0x78) >> 3;
-}
-
-static FORCEINLINE uint8_t RegisterFromIS4(uint8_t is4) {
-  return is4 >> 4;
-}
-
-static const uint8_t index_registers[] = {
-  /* Note how REG_RIZ falls out of the pattern. */
-  REG_RAX, REG_RCX, REG_RDX, REG_RBX,
-  REG_RIZ, REG_RBP, REG_RSI, REG_RDI,
-  REG_R8,  REG_R9,  REG_R10, REG_R11,
-  REG_R12, REG_R13, REG_R14, REG_R15
+enum imm_mode {
+  IMMNONE,
+  IMM2,
+  IMM8,
+  IMM16,
+  IMM32,
+  IMM64
 };
 
 #endif  /* NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODER_INTERNAL_H_ */