[MIPS] Implementation of sel_ldr for MIPS architecture.

src/trusted/platform_qualify/arch/mips/nacl_dep_qualify_arch.c

Index: src/trusted/platform_qualify/arch/mips/nacl_dep_qualify_arch.c
diff --git a/src/trusted/platform_qualify/arch/arm/nacl_dep_qualify_arch.c b/src/trusted/platform_qualify/arch/mips/nacl_dep_qualify_arch.c
similarity index 51%
copy from src/trusted/platform_qualify/arch/arm/nacl_dep_qualify_arch.c
copy to src/trusted/platform_qualify/arch/mips/nacl_dep_qualify_arch.c
index 3d6d3531ef0880d80829d644cc9de00ccdcc1f0d..7b8b61039447ab54d23526a5683af70969dbe1a0 100644
--- a/src/trusted/platform_qualify/arch/arm/nacl_dep_qualify_arch.c
+++ b/src/trusted/platform_qualify/arch/mips/nacl_dep_qualify_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 The Native Client Authors.  All rights reserved.
+ * Copyright 2012 The Native Client Authors.  All rights reserved.

[Mark Seaborn, 2012/09/08 02:43:14]

BTW, we don't update the copyright year any more.  See the recent chromium-dev
post on the topic.

[petarj, 2012/09/11 16:58:13]

As I understand from there, when a new file is created, the current year is set.
This is a new file, even though it may not be so obvious when the review site
offers a comparison with a similar file.

  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
@@ -9,29 +9,35 @@
 #include "native_client/src/trusted/platform_qualify/nacl_dep_qualify.h"
 #include "native_client/src/include/nacl_macros.h"
 
-/* Assembled equivalent of "bx lr" */
-#define INST_BX_LR 0xE12FFF1E
+/* Assembled equivalent of "jr ra" */
+#define INST_JR_RA 0x3E00008
+#define INST_NOP   0x0000000
 
 int NaClCheckDEP() {
   /*
    * We require DEP, so forward this call to the OS-specific check routine.
    */
-  return NaClAttemptToExecuteData();
+   return NaClAttemptToExecuteData();

[Mark Seaborn, 2012/09/08 02:43:14]

Nit: the changed indentation here is wrong

[petarj, 2012/09/11 16:58:13]

Done.

 }
 
 nacl_void_thunk NaClGenerateThunk(char *buf, size_t size_in_bytes) {
   /*
-   * Place a "bx lr" at the next aligned address after buf.  Instructions
-   * are always little-endian, regardless of data setting.
+   * Place a "jr ra" at the next aligned address after buf.  Instructions
+   * are always little-endian, regardless of data setting. We also place opcode
+   * for "nop" (which is zero) because of delay slot in Mips.
    */
   char *aligned_buf = (char *) (((uintptr_t) buf + 3) & ~3);
 
-  if (aligned_buf + 4 > buf + size_in_bytes) return 0;
+  if (aligned_buf + 8 > buf + size_in_bytes) return 0;
 
-  aligned_buf[0] = (char) (INST_BX_LR >> 0);
-  aligned_buf[1] = (char) (INST_BX_LR >> 8);
-  aligned_buf[2] = (char) (INST_BX_LR >> 16);
-  aligned_buf[3] = (char) (INST_BX_LR >> 24);
+  aligned_buf[0] = (char) (INST_JR_RA >> 0);

[Mark Seaborn, 2012/09/08 02:43:14]

Why not just write:

uint32_t *aligned_buf = ...;
aligned_buf[0] = INST_JR_RA;
aligned_buf[1] = INST_NOP;

The ARM case might be made unnecessarily complex but you don't need to copy
that.

[petarj, 2012/09/11 16:58:13]

Done.

+  aligned_buf[1] = (char) (INST_JR_RA >> 8);
+  aligned_buf[2] = (char) (INST_JR_RA >> 16);
+  aligned_buf[3] = (char) (INST_JR_RA >> 24);
+  aligned_buf[4] = (char) (INST_NOP >> 0);
+  aligned_buf[5] = (char) (INST_NOP >> 8);
+  aligned_buf[6] = (char) (INST_NOP >> 16);
+  aligned_buf[7] = (char) (INST_NOP >> 24);
 
   /*
    * ISO C prevents a direct data->function cast, because the pointers aren't