Refactor Math.min/max to be a single HInstruction.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 113 matching lines @@
   void DecodeType01(Instruction* instr);
   void DecodeType2(Instruction* instr);
   void DecodeType3(Instruction* instr);
   void DecodeType4(Instruction* instr);
   void DecodeType5(Instruction* instr);
   void DecodeType6(Instruction* instr);
   // Type 7 includes special Debugger instructions.
   int DecodeType7(Instruction* instr);
   // For VFP support.
   void DecodeTypeVFP(Instruction* instr);
+  void DecodeSpecialCondition(Instruction* instr);
   void DecodeType6CoprocessorIns(Instruction* instr);
 
   void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr);
   void DecodeVCMP(Instruction* instr);
   void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr);
   void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr);
 
   const disasm::NameConverter& converter_;
   Vector<char> out_buffer_;
   int out_buffer_pos_;
@@ skipping 1060 matching lines @@
       Format(instr, "vcmp.f64'cond 'Dd, #0.0");
     } else {
       Unknown(instr);  // invalid
     }
   } else {
     Unknown(instr);  // Not used by V8.
   }
 }
 
 
+// Currently supports:
+// Dd = vorr(Dn, Dm)
+void Decoder::DecodeSpecialCondition(Instruction* instr) {
+  // See ARM DDI 0406A, A7-12 for how to detect which instruction this is.
+  if (instr->Bits(11, 8) == 0x1 &&
+      instr->Bit(4) == 0x1 &&
+      instr->Bit(24) == 0x0 &&
+      instr->Opc1Value() == 0x2) {

[Erik Corry, 2012/08/06 10:44:40]

This tests bits 20, 21, 23, 24, but ignores bits 25-27 and 22 and 4-7.  Should
it not say 'Unknown' if they do not match the expectations for vorr?

[Jakob Kummerow, 2012/08/06 14:08:43]

As discussed, removed vorr completely.

+    // vorr
+    Format(instr, "vorr 'Dd, 'Dn, 'Dm");
+  } else {
+    Unknown(instr);
+  }
+}
+
+
 void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
   VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
   VERIFY((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
 
   bool double_to_single = (instr->SzValue() == 1);
 
   if (double_to_single) {
     Format(instr, "vcvt.f32.f64'cond 'Sd, 'Dm");
   } else {
     Format(instr, "vcvt.f64.f32'cond 'Dd, 'Sm");
@@ skipping 151 matching lines @@
 
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
 int Decoder::InstructionDecode(byte* instr_ptr) {
   Instruction* instr = Instruction::At(instr_ptr);
   // Print raw instruction bytes.
   out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                   "%08x       ",
                                   instr->InstructionBits());
   if (instr->ConditionField() == kSpecialCondition) {
-    Unknown(instr);
+    DecodeSpecialCondition(instr);
     return Instruction::kInstrSize;
   }
   int instruction_bits = *(reinterpret_cast<int*>(instr_ptr));
   if ((instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker) {
     out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "constant pool begin (length %d)",
                                     instruction_bits &
                                     kConstantPoolLengthMask);
     return Instruction::kInstrSize;
   }
@@ skipping 111 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM