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Issue 10818026: Relax requirement from VFP3 to VFP2 where possible. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 8 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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429 // feel free to change this if needed.) 429 // feel free to change this if needed.)
430 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. 430 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX.
431 enum CpuFeature { SSE4_1 = 32 + 19, // x86 431 enum CpuFeature { SSE4_1 = 32 + 19, // x86
432 SSE3 = 32 + 0, // x86 432 SSE3 = 32 + 0, // x86
433 SSE2 = 26, // x86 433 SSE2 = 26, // x86
434 CMOV = 15, // x86 434 CMOV = 15, // x86
435 RDTSC = 4, // x86 435 RDTSC = 4, // x86
436 CPUID = 10, // x86 436 CPUID = 10, // x86
437 VFP3 = 1, // ARM 437 VFP3 = 1, // ARM
438 ARMv7 = 2, // ARM 438 ARMv7 = 2, // ARM
439 VFP2 = 3, // ARM
439 SAHF = 0, // x86 440 SAHF = 0, // x86
440 FPU = 1}; // MIPS 441 FPU = 1}; // MIPS
441 442
442 443
443 // Used to specify if a macro instruction must perform a smi check on tagged 444 // Used to specify if a macro instruction must perform a smi check on tagged
444 // values. 445 // values.
445 enum SmiCheckType { 446 enum SmiCheckType {
446 DONT_DO_SMI_CHECK, 447 DONT_DO_SMI_CHECK,
447 DO_SMI_CHECK 448 DO_SMI_CHECK
448 }; 449 };
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547 548
548 enum ClearExceptionFlag { 549 enum ClearExceptionFlag {
549 KEEP_EXCEPTION, 550 KEEP_EXCEPTION,
550 CLEAR_EXCEPTION 551 CLEAR_EXCEPTION
551 }; 552 };
552 553
553 554
554 } } // namespace v8::internal 555 } } // namespace v8::internal
555 556
556 #endif // V8_V8GLOBALS_H_ 557 #endif // V8_V8GLOBALS_H_
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