Fix cases where fast instruction selection generated both base and index registers

llvm/lib/Target/X86/X86FastISel.cpp

Index: llvm/lib/Target/X86/X86FastISel.cpp
===================================================================
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -578,15 +578,17 @@
 
   // If all else fails, try to materialize the value in a register.
   if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
-    if (AM.Base.Reg == 0) {
-      AM.Base.Reg = getRegForValue(V);
-      return AM.Base.Reg != 0;
-    }
-    if (AM.IndexReg == 0) {
-      assert(AM.Scale == 1 && "Scale with no index!");
+    // @LOCALMOD-START
+    // We can materialize into a memory address only if
+    // no registers have been defined (and hence, we
+    // aren't modifying an existing memory reference).
+    if ((AM.Base.Reg == 0) && (AM.IndexReg == 0)) {

[jvoung - send to chromium..., 2012/07/24 21:08:35]

You can avoid changing the original behavior for non-NaCl targets, by checking
if we are generating code for NaCl first.  E.g.,:


"if (Subtarget->isTargetNaCl()) {
  ... localmod ...
} else {
  ... original code ...
}"

Then it also makes more obvious what the difference is.

[Karl, 2012/07/24 22:05:30]

Done.

+      // Put into index register so that the NaCl rewrite pass will
+      // convert this to a 64-bit address.
       AM.IndexReg = getRegForValue(V);
       return AM.IndexReg != 0;
     }
+    // @LOCALMOD-END
   }
 
   return false;