Add tzcnt as an acceptable instruction to x86-64 validator (it already

src/trusted/validator/x86/decoder/generator/ncdecode_sse.c

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that be
  * found in the LICENSE file.
  */
 
 /*
  * Defines SSE instructions. Taken from:
  * (1) Tables A-3 and A-4 of appendix "A2 - Opcode Encodings", in AMD
  *     document 24594-Rev.3.14-September 2007: "AMD64 Architecture
@@ skipping 311 matching lines @@
   NaClDefine("   f20f79:     Insertq $Vdq, $VRdq", NACLi_SSE4A,   st, Binary);
   NaClDefIter("  f20f7a+@i:  Invalid", 0, 1,       NACLi_INVALID, st, Other);
   NaClDefine("   f20f7c:     Haddps $Vps, $Wps",   NACLi_SSE3,    st, Binary);
   NaClDefine("   f20f7d:     Hsubps $Vps, $Wps",   NACLi_SSE3,    st, Binary);
   NaClDefIter("  f20f7e+@i:  Invalid", 0, 1,       NACLi_INVALID, st, Other);
   NaClDefIter("  f30f78+@i:  Invalid", 0, 5,       NACLi_INVALID, st, Other);
   NaClDefine("   f30f7e:     Movq $Vq, $Wq",       NACLi_SSE2,    st, Move);
   NaClDefine("   f30f7f:     Movdqu $Wdq, $Vdq",   NACLi_SSE2,    st, Move);
   NaClDefIter("  f20fb8+@i:  Invalid", 0, 7,       NACLi_INVALID, st, Other);
   NaClDefine("   f30fb8:     Popcnt $Gv, $Ev",     NACLi_POPCNT,  st, Move);
-  NaClDefIter("  f30fb9+@i:  Invalid", 0, 3,       NACLi_INVALID, st, Other);
-  NaClDefine("   f30fbd:     Lzcnt $Gv, $Ev",      NACLi_LZCNT,   st, Move);
+  NaClDefIter("  f30fb9+@i:  Invalid", 0, 2,       NACLi_INVALID, st, Other);
+  /* tzcnt is treated as a bsf on machines that don't have tzcnt.
+   * Hence, even though its conditional on NACLi_LZCNT, we act
+   * like it can be used on all processors.
+   */
+  NaClDefine("   f30fbc:     Tzcnt $Gv, $Ev",      NACLi_386,     st, Move);

[Karl, 2012/07/24 21:28:18]

Made tzcnt and lzcnt work on all processors.

+  /* lzcnt is treated as a bsr on machines that don't have lzcnt.
+   * Hence, even though its conditional on NACLi_LZCNT, we act
+   * like it can be used on all processors.
+   */
+  NaClDefine("   f30fbd:     Lzcnt $Gv, $Ev",      NACLi_386,     st, Move);
   NaClDefIter("  f30fbe+@i:  Invalid", 0, 1,       NACLi_INVALID, st, Other);
   NaClDefine("     0fc2:     Cmpps $Vps, $Wps, $Ib",
                                                    NACLi_SSE,     st, Nary);
   NaClDefine("     0fc3:     Movnti $Md/q $Gd/q",  NACLi_SSE2,    st, Move);
   /* Note: Pinsrw follows Intel's table, not ADM, which uses:
    *    Pinsrw $Pq, $Ew, $Ib
    */
   NaClDefine("     0fc4:     Pinsrw $Pq, $Rd/q/Mw, $Ib",
                                                    NACLi_SSE,     st, Nary);
   NaClDefine("     0fc5:     Pextrw $Gd, $PRq, $Ib",
@@ skipping 254 matching lines @@
                                                    NACLi_SSE42,   st, O1Nary);
   NaClDefine(" 660f3a63:     Pcmpistri {$rCXv}, $Vdq, $Wdq, $Ib",
                                                    NACLi_SSE42,   st, O1Nary);
 }
 
 void NaClDefSseInsts(struct NaClSymbolTable* st) {
   NaClDefNarySseInsts(st);
   NaClDefBinarySseInsts(st);
   NaClDefMmxInsts(st);
 }