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Side by Side Diff: src/trusted/validator/x86/decoder/gen/nc_opcode_table_64.h

Issue 10790077: Add tzcnt as an acceptable instruction to x86-64 validator (it already (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 5 months ago
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1 /* 1 /*
2 * THIS FILE IS AUTO-GENERATED. DO NOT EDIT. 2 * THIS FILE IS AUTO-GENERATED. DO NOT EDIT.
3 * Compiled for x86-64 bit mode. 3 * Compiled for x86-64 bit mode.
4 * 4 *
5 * You must include ncopcode_desc.h before this file. 5 * You must include ncopcode_desc.h before this file.
6 */ 6 */
7 7
8 static const NaClOp g_Operands[735] = { 8 static const NaClOp g_Operands[735] = {
9 /* 0 */ { E_Operand, NACL_OPFLAG(OpUse) | NACL_OPFLAG(OpSet), "$Eb" }, 9 /* 0 */ { E_Operand, NACL_OPFLAG(OpUse) | NACL_OPFLAG(OpSet), "$Eb" },
10 /* 1 */ { G_Operand, NACL_OPFLAG(OpUse), "$Gb" }, 10 /* 1 */ { G_Operand, NACL_OPFLAG(OpUse), "$Gb" },
(...skipping 725 matching lines...) Expand 10 before | Expand all | Expand 10 after
736 /* 727 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" }, 736 /* 727 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" },
737 /* 728 */ { RegST5, NACL_OPFLAG(OpSet), "%st5" }, 737 /* 728 */ { RegST5, NACL_OPFLAG(OpSet), "%st5" },
738 /* 729 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" }, 738 /* 729 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" },
739 /* 730 */ { RegST6, NACL_OPFLAG(OpSet), "%st6" }, 739 /* 730 */ { RegST6, NACL_OPFLAG(OpSet), "%st6" },
740 /* 731 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" }, 740 /* 731 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" },
741 /* 732 */ { RegST7, NACL_OPFLAG(OpSet), "%st7" }, 741 /* 732 */ { RegST7, NACL_OPFLAG(OpSet), "%st7" },
742 /* 733 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" }, 742 /* 733 */ { RegST0, NACL_OPFLAG(OpUse), "%st0" },
743 /* 734 */ { RegAX, NACL_OPFLAG(OpSet), "%ax" }, 743 /* 734 */ { RegAX, NACL_OPFLAG(OpSet), "%ax" },
744 }; 744 };
745 745
746 static const NaClInst g_Opcodes[1340] = { 746 static const NaClInst g_Opcodes[1341] = {
747 /* 0 */ 747 /* 0 */
748 { NACLi_INVALID, 748 { NACLi_INVALID,
749 NACL_EMPTY_IFLAGS, 749 NACL_EMPTY_IFLAGS,
750 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 750 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
751 /* 1 */ 751 /* 1 */
752 { NACLi_386, 752 { NACLi_386,
753 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeLockable) | NACL_IFLAG(Operan dSize_b), 753 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeLockable) | NACL_IFLAG(Operan dSize_b),
754 InstAdd, 0x00, 2, 0, NACL_OPCODE_NULL_OFFSET }, 754 InstAdd, 0x00, 2, 0, NACL_OPCODE_NULL_OFFSET },
755 /* 2 */ 755 /* 2 */
756 { NACLi_386, 756 { NACLi_386,
(...skipping 2957 matching lines...) Expand 10 before | Expand all | Expand 10 after
3714 InstMovq, 0x00, 2, 447, NACL_OPCODE_NULL_OFFSET }, 3714 InstMovq, 0x00, 2, 447, NACL_OPCODE_NULL_OFFSET },
3715 /* 742 */ 3715 /* 742 */
3716 { NACLi_SSE2, 3716 { NACLi_SSE2,
3717 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep), 3717 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep),
3718 InstMovdqu, 0x00, 2, 485, NACL_OPCODE_NULL_OFFSET }, 3718 InstMovdqu, 0x00, 2, 485, NACL_OPCODE_NULL_OFFSET },
3719 /* 743 */ 3719 /* 743 */
3720 { NACLi_POPCNT, 3720 { NACLi_POPCNT,
3721 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o), 3721 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o),
3722 InstPopcnt, 0x00, 2, 340, NACL_OPCODE_NULL_OFFSET }, 3722 InstPopcnt, 0x00, 2, 340, NACL_OPCODE_NULL_OFFSET },
3723 /* 744 */ 3723 /* 744 */
3724 { NACLi_LZCNT, 3724 { NACLi_386,
3725 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o),
3726 InstTzcnt, 0x00, 2, 340, NACL_OPCODE_NULL_OFFSET },
3727 /* 745 */
3728 { NACLi_386,
3725 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o), 3729 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o),
3726 InstLzcnt, 0x00, 2, 340, NACL_OPCODE_NULL_OFFSET }, 3730 InstLzcnt, 0x00, 2, 340, NACL_OPCODE_NULL_OFFSET },
3727 /* 745 */ 3731 /* 746 */
3728 { NACLi_SSE, 3732 { NACLi_SSE,
3729 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsRep), 3733 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsRep),
3730 InstCmpss, 0x00, 3, 487, NACL_OPCODE_NULL_OFFSET }, 3734 InstCmpss, 0x00, 3, 487, NACL_OPCODE_NULL_OFFSET },
3731 /* 746 */ 3735 /* 747 */
3732 { NACLi_SSE2, 3736 { NACLi_SSE2,
3733 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsRep), 3737 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsRep),
3734 InstMovq2dq, 0x00, 2, 490, NACL_OPCODE_NULL_OFFSET }, 3738 InstMovq2dq, 0x00, 2, 490, NACL_OPCODE_NULL_OFFSET },
3735 /* 747 */ 3739 /* 748 */
3736 { NACLi_SSE2, 3740 { NACLi_SSE2,
3737 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep), 3741 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRep),
3738 InstCvtdq2pd, 0x00, 2, 492, NACL_OPCODE_NULL_OFFSET }, 3742 InstCvtdq2pd, 0x00, 2, 492, NACL_OPCODE_NULL_OFFSET },
3739 /* 748 */ 3743 /* 749 */
3740 { NACLi_SSE2, 3744 { NACLi_SSE2,
3741 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3745 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3742 InstMovupd, 0x00, 2, 494, NACL_OPCODE_NULL_OFFSET }, 3746 InstMovupd, 0x00, 2, 494, NACL_OPCODE_NULL_OFFSET },
3743 /* 749 */ 3747 /* 750 */
3744 { NACLi_SSE2, 3748 { NACLi_SSE2,
3745 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3749 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3746 InstMovupd, 0x00, 2, 496, NACL_OPCODE_NULL_OFFSET }, 3750 InstMovupd, 0x00, 2, 496, NACL_OPCODE_NULL_OFFSET },
3747 /* 750 */ 3751 /* 751 */
3748 { NACLi_SSE2, 3752 { NACLi_SSE2,
3749 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3753 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3750 InstMovlpd, 0x00, 2, 498, NACL_OPCODE_NULL_OFFSET }, 3754 InstMovlpd, 0x00, 2, 498, NACL_OPCODE_NULL_OFFSET },
3751 /* 751 */ 3755 /* 752 */
3752 { NACLi_SSE2, 3756 { NACLi_SSE2,
3753 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3757 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3754 InstMovlpd, 0x00, 2, 439, NACL_OPCODE_NULL_OFFSET }, 3758 InstMovlpd, 0x00, 2, 439, NACL_OPCODE_NULL_OFFSET },
3755 /* 752 */ 3759 /* 753 */
3756 { NACLi_SSE2, 3760 { NACLi_SSE2,
3757 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3761 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3758 InstUnpcklpd, 0x00, 2, 500, NACL_OPCODE_NULL_OFFSET }, 3762 InstUnpcklpd, 0x00, 2, 500, NACL_OPCODE_NULL_OFFSET },
3759 /* 753 */ 3763 /* 754 */
3760 { NACLi_SSE2, 3764 { NACLi_SSE2,
3761 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3765 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3762 InstUnpckhpd, 0x00, 2, 500, NACL_OPCODE_NULL_OFFSET }, 3766 InstUnpckhpd, 0x00, 2, 500, NACL_OPCODE_NULL_OFFSET },
3763 /* 754 */ 3767 /* 755 */
3764 { NACLi_SSE2, 3768 { NACLi_SSE2,
3765 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3769 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3766 InstMovhpd, 0x00, 2, 498, NACL_OPCODE_NULL_OFFSET }, 3770 InstMovhpd, 0x00, 2, 498, NACL_OPCODE_NULL_OFFSET },
3767 /* 755 */ 3771 /* 756 */
3768 { NACLi_SSE2, 3772 { NACLi_SSE2,
3769 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3773 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3770 InstMovhpd, 0x00, 2, 439, NACL_OPCODE_NULL_OFFSET }, 3774 InstMovhpd, 0x00, 2, 439, NACL_OPCODE_NULL_OFFSET },
3771 /* 756 */ 3775 /* 757 */
3772 { NACLi_SSE2, 3776 { NACLi_SSE2,
3773 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3777 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3774 InstMovapd, 0x00, 2, 494, NACL_OPCODE_NULL_OFFSET }, 3778 InstMovapd, 0x00, 2, 494, NACL_OPCODE_NULL_OFFSET },
3775 /* 757 */ 3779 /* 758 */
3776 { NACLi_SSE2, 3780 { NACLi_SSE2,
3777 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3781 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3778 InstMovapd, 0x00, 2, 496, NACL_OPCODE_NULL_OFFSET }, 3782 InstMovapd, 0x00, 2, 496, NACL_OPCODE_NULL_OFFSET },
3779 /* 758 */ 3783 /* 759 */
3780 { NACLi_SSE2, 3784 { NACLi_SSE2,
3781 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3785 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3782 InstCvtpi2pd, 0x00, 2, 502, NACL_OPCODE_NULL_OFFSET }, 3786 InstCvtpi2pd, 0x00, 2, 502, NACL_OPCODE_NULL_OFFSET },
3783 /* 759 */ 3787 /* 760 */
3784 { NACLi_SSE2, 3788 { NACLi_SSE2,
3785 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3789 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3786 InstMovntpd, 0x00, 2, 504, NACL_OPCODE_NULL_OFFSET }, 3790 InstMovntpd, 0x00, 2, 504, NACL_OPCODE_NULL_OFFSET },
3787 /* 760 */ 3791 /* 761 */
3788 { NACLi_SSE2, 3792 { NACLi_SSE2,
3789 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3793 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3790 InstCvttpd2pi, 0x00, 2, 506, NACL_OPCODE_NULL_OFFSET }, 3794 InstCvttpd2pi, 0x00, 2, 506, NACL_OPCODE_NULL_OFFSET },
3791 /* 761 */ 3795 /* 762 */
3792 { NACLi_SSE2, 3796 { NACLi_SSE2,
3793 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3797 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3794 InstCvtpd2pi, 0x00, 2, 506, NACL_OPCODE_NULL_OFFSET }, 3798 InstCvtpd2pi, 0x00, 2, 506, NACL_OPCODE_NULL_OFFSET },
3795 /* 762 */ 3799 /* 763 */
3796 { NACLi_SSE2, 3800 { NACLi_SSE2,
3797 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3801 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3798 InstUcomisd, 0x00, 2, 508, NACL_OPCODE_NULL_OFFSET }, 3802 InstUcomisd, 0x00, 2, 508, NACL_OPCODE_NULL_OFFSET },
3799 /* 763 */ 3803 /* 764 */
3800 { NACLi_SSE2, 3804 { NACLi_SSE2,
3801 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3805 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3802 InstComisd, 0x00, 2, 510, NACL_OPCODE_NULL_OFFSET }, 3806 InstComisd, 0x00, 2, 510, NACL_OPCODE_NULL_OFFSET },
3803 /* 764 */ 3807 /* 765 */
3804 { NACLi_SSE2, 3808 { NACLi_SSE2,
3805 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16), 3809 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16),
3806 InstMovmskpd, 0x00, 2, 512, NACL_OPCODE_NULL_OFFSET }, 3810 InstMovmskpd, 0x00, 2, 512, NACL_OPCODE_NULL_OFFSET },
3807 /* 765 */ 3811 /* 766 */
3808 { NACLi_SSE2, 3812 { NACLi_SSE2,
3809 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3813 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3810 InstSqrtpd, 0x00, 2, 514, NACL_OPCODE_NULL_OFFSET }, 3814 InstSqrtpd, 0x00, 2, 514, NACL_OPCODE_NULL_OFFSET },
3811 /* 766 */ 3815 /* 767 */
3812 { NACLi_INVALID, 3816 { NACLi_INVALID,
3813 NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG( NaClIllegal), 3817 NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG( NaClIllegal),
3814 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 3818 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
3815 /* 767 */ 3819 /* 768 */
3816 { NACLi_SSE2, 3820 { NACLi_SSE2,
3817 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3821 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3818 InstAndpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3822 InstAndpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3819 /* 768 */ 3823 /* 769 */
3820 { NACLi_SSE2, 3824 { NACLi_SSE2,
3821 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3825 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3822 InstAndnpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3826 InstAndnpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3823 /* 769 */ 3827 /* 770 */
3824 { NACLi_SSE2, 3828 { NACLi_SSE2,
3825 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3829 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3826 InstOrpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3830 InstOrpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3827 /* 770 */ 3831 /* 771 */
3828 { NACLi_SSE2, 3832 { NACLi_SSE2,
3829 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3833 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3830 InstXorpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3834 InstXorpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3831 /* 771 */ 3835 /* 772 */
3832 { NACLi_SSE2, 3836 { NACLi_SSE2,
3833 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3837 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3834 InstAddpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3838 InstAddpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3835 /* 772 */ 3839 /* 773 */
3836 { NACLi_SSE2, 3840 { NACLi_SSE2,
3837 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3841 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3838 InstMulpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3842 InstMulpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3839 /* 773 */ 3843 /* 774 */
3840 { NACLi_SSE2, 3844 { NACLi_SSE2,
3841 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3845 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3842 InstCvtpd2ps, 0x00, 2, 514, NACL_OPCODE_NULL_OFFSET }, 3846 InstCvtpd2ps, 0x00, 2, 514, NACL_OPCODE_NULL_OFFSET },
3843 /* 774 */ 3847 /* 775 */
3844 { NACLi_SSE2, 3848 { NACLi_SSE2,
3845 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3849 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3846 InstCvtps2dq, 0x00, 2, 481, NACL_OPCODE_NULL_OFFSET }, 3850 InstCvtps2dq, 0x00, 2, 481, NACL_OPCODE_NULL_OFFSET },
3847 /* 775 */ 3851 /* 776 */
3848 { NACLi_SSE2, 3852 { NACLi_SSE2,
3849 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3853 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3850 InstSubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3854 InstSubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3851 /* 776 */ 3855 /* 777 */
3852 { NACLi_SSE2, 3856 { NACLi_SSE2,
3853 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3857 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3854 InstMinpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3858 InstMinpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3855 /* 777 */ 3859 /* 778 */
3856 { NACLi_SSE2, 3860 { NACLi_SSE2,
3857 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3861 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3858 InstDivpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3862 InstDivpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3859 /* 778 */ 3863 /* 779 */
3860 { NACLi_SSE2, 3864 { NACLi_SSE2,
3861 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3865 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3862 InstMaxpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 3866 InstMaxpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
3863 /* 779 */ 3867 /* 780 */
3864 { NACLi_SSE2, 3868 { NACLi_SSE2,
3865 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3869 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3866 InstPunpcklbw, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3870 InstPunpcklbw, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3867 /* 780 */ 3871 /* 781 */
3868 { NACLi_SSE2, 3872 { NACLi_SSE2,
3869 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3873 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3870 InstPunpcklwd, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3874 InstPunpcklwd, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3871 /* 781 */ 3875 /* 782 */
3872 { NACLi_SSE2, 3876 { NACLi_SSE2,
3873 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3877 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3874 InstPunpckldq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3878 InstPunpckldq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3875 /* 782 */ 3879 /* 783 */
3876 { NACLi_SSE2, 3880 { NACLi_SSE2,
3877 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3881 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3878 InstPacksswb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3882 InstPacksswb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3879 /* 783 */ 3883 /* 784 */
3880 { NACLi_SSE2, 3884 { NACLi_SSE2,
3881 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3885 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3882 InstPcmpgtb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3886 InstPcmpgtb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3883 /* 784 */ 3887 /* 785 */
3884 { NACLi_SSE2, 3888 { NACLi_SSE2,
3885 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3889 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3886 InstPcmpgtw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3890 InstPcmpgtw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3887 /* 785 */ 3891 /* 786 */
3888 { NACLi_SSE2, 3892 { NACLi_SSE2,
3889 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3893 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3890 InstPcmpgtd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3894 InstPcmpgtd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3891 /* 786 */ 3895 /* 787 */
3892 { NACLi_SSE2, 3896 { NACLi_SSE2,
3893 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3897 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3894 InstPackuswb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3898 InstPackuswb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3895 /* 787 */ 3899 /* 788 */
3896 { NACLi_SSE2, 3900 { NACLi_SSE2,
3897 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3901 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3898 InstPunpckhbw, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3902 InstPunpckhbw, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3899 /* 788 */ 3903 /* 789 */
3900 { NACLi_SSE2, 3904 { NACLi_SSE2,
3901 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3905 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3902 InstPunpckhwd, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3906 InstPunpckhwd, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3903 /* 789 */ 3907 /* 790 */
3904 { NACLi_SSE2, 3908 { NACLi_SSE2,
3905 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3909 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3906 InstPunpckhdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3910 InstPunpckhdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3907 /* 790 */ 3911 /* 791 */
3908 { NACLi_SSE2, 3912 { NACLi_SSE2,
3909 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3913 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3910 InstPackssdw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 3914 InstPackssdw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
3911 /* 791 */ 3915 /* 792 */
3912 { NACLi_SSE2, 3916 { NACLi_SSE2,
3913 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3917 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3914 InstPunpcklqdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3918 InstPunpcklqdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3915 /* 792 */ 3919 /* 793 */
3916 { NACLi_SSE2, 3920 { NACLi_SSE2,
3917 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3921 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3918 InstPunpckhqdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET }, 3922 InstPunpckhqdq, 0x00, 2, 516, NACL_OPCODE_NULL_OFFSET },
3919 /* 793 */ 3923 /* 794 */
3920 { NACLi_SSE2, 3924 { NACLi_SSE2,
3921 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_o), 3925 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_o),
3922 InstMovq, 0x00, 2, 520, NACL_OPCODE_NULL_OFFSET }, 3926 InstMovq, 0x00, 2, 520, NACL_OPCODE_NULL_OFFSET },
3923 /* 794 */ 3927 /* 795 */
3924 { NACLi_SSE2, 3928 { NACLi_SSE2,
3925 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_v), 3929 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_v),
3926 InstMovd, 0x00, 2, 522, 793 }, 3930 InstMovd, 0x00, 2, 522, 794 },
3927 /* 795 */ 3931 /* 796 */
3928 { NACLi_SSE2, 3932 { NACLi_SSE2,
3929 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 3933 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
3930 InstMovdqa, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET }, 3934 InstMovdqa, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET },
3931 /* 796 */ 3935 /* 797 */
3932 { NACLi_SSE2, 3936 { NACLi_SSE2,
3933 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 3937 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
3934 InstPshufd, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET }, 3938 InstPshufd, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET },
3935 /* 797 */ 3939 /* 798 */
3936 { NACLi_INVALID, 3940 { NACLi_INVALID,
3937 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3941 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3938 InstInvalid, 0x07, 0, 0, NACL_OPCODE_NULL_OFFSET }, 3942 InstInvalid, 0x07, 0, 0, NACL_OPCODE_NULL_OFFSET },
3939 /* 798 */ 3943 /* 799 */
3940 { NACLi_SSE2, 3944 { NACLi_SSE2,
3941 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16), 3945 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3942 InstPsllw, 0x06, 2, 527, 797 }, 3946 InstPsllw, 0x06, 2, 527, 798 },
3943 /* 799 */ 3947 /* 800 */
3944 { NACLi_INVALID, 3948 { NACLi_INVALID,
3945 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3949 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3946 InstInvalid, 0x05, 0, 0, 798 }, 3950 InstInvalid, 0x05, 0, 0, 799 },
3947 /* 800 */ 3951 /* 801 */
3948 { NACLi_SSE2, 3952 { NACLi_SSE2,
3949 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16), 3953 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3950 InstPsraw, 0x04, 2, 527, 799 }, 3954 InstPsraw, 0x04, 2, 527, 800 },
3951 /* 801 */ 3955 /* 802 */
3952 { NACLi_INVALID, 3956 { NACLi_INVALID,
3953 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3957 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3954 InstInvalid, 0x03, 0, 0, 800 }, 3958 InstInvalid, 0x03, 0, 0, 801 },
3955 /* 802 */ 3959 /* 803 */
3956 { NACLi_SSE2, 3960 { NACLi_SSE2,
3957 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16), 3961 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3958 InstPsrlw, 0x02, 2, 527, 801 }, 3962 InstPsrlw, 0x02, 2, 527, 802 },
3959 /* 803 */
3960 { NACLi_INVALID,
3961 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3962 InstInvalid, 0x01, 0, 0, 802 },
3963 /* 804 */ 3963 /* 804 */
3964 { NACLi_INVALID, 3964 { NACLi_INVALID,
3965 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3965 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3966 InstInvalid, 0x00, 0, 0, 803 }, 3966 InstInvalid, 0x01, 0, 0, 803 },
3967 /* 805 */ 3967 /* 805 */
3968 { NACLi_SSE2,
3969 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3970 InstPslld, 0x06, 2, 527, 797 },
3971 /* 806 */
3972 { NACLi_INVALID, 3968 { NACLi_INVALID,
3973 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3969 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3974 InstInvalid, 0x05, 0, 0, 805 }, 3970 InstInvalid, 0x00, 0, 0, 804 },
3971 /* 806 */
3972 { NACLi_SSE2,
3973 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3974 InstPslld, 0x06, 2, 527, 798 },
3975 /* 807 */ 3975 /* 807 */
3976 { NACLi_SSE2,
3977 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3978 InstPsrad, 0x04, 2, 527, 806 },
3979 /* 808 */
3980 { NACLi_INVALID, 3976 { NACLi_INVALID,
3981 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3977 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3982 InstInvalid, 0x03, 0, 0, 807 }, 3978 InstInvalid, 0x05, 0, 0, 806 },
3979 /* 808 */
3980 { NACLi_SSE2,
3981 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3982 InstPsrad, 0x04, 2, 527, 807 },
3983 /* 809 */ 3983 /* 809 */
3984 { NACLi_SSE2,
3985 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3986 InstPsrld, 0x02, 2, 527, 808 },
3987 /* 810 */
3988 { NACLi_INVALID, 3984 { NACLi_INVALID,
3989 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3985 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3990 InstInvalid, 0x01, 0, 0, 809 }, 3986 InstInvalid, 0x03, 0, 0, 808 },
3987 /* 810 */
3988 { NACLi_SSE2,
3989 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3990 InstPsrld, 0x02, 2, 527, 809 },
3991 /* 811 */ 3991 /* 811 */
3992 { NACLi_INVALID, 3992 { NACLi_INVALID,
3993 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 3993 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3994 InstInvalid, 0x00, 0, 0, 810 }, 3994 InstInvalid, 0x01, 0, 0, 810 },
3995 /* 812 */ 3995 /* 812 */
3996 { NACLi_INVALID,
3997 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
3998 InstInvalid, 0x00, 0, 0, 811 },
3999 /* 813 */
3996 { NACLi_SSE2, 4000 { NACLi_SSE2,
3997 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16), 4001 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
3998 InstPslldq, 0x07, 2, 527, NACL_OPCODE_NULL_OFFSET }, 4002 InstPslldq, 0x07, 2, 527, NACL_OPCODE_NULL_OFFSET },
3999 /* 813 */ 4003 /* 814 */
4000 { NACLi_SSE2, 4004 { NACLi_SSE2,
4001 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16), 4005 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
4002 InstPsllq, 0x06, 2, 527, 812 }, 4006 InstPsllq, 0x06, 2, 527, 813 },
4003 /* 814 */
4004 { NACLi_INVALID,
4005 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4006 InstInvalid, 0x05, 0, 0, 813 },
4007 /* 815 */ 4007 /* 815 */
4008 { NACLi_INVALID, 4008 { NACLi_INVALID,
4009 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4009 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4010 InstInvalid, 0x04, 0, 0, 814 }, 4010 InstInvalid, 0x05, 0, 0, 814 },
4011 /* 816 */ 4011 /* 816 */
4012 { NACLi_SSE2,
4013 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
4014 InstPsrldq, 0x03, 2, 527, 815 },
4015 /* 817 */
4016 { NACLi_SSE2,
4017 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
4018 InstPsrlq, 0x02, 2, 527, 816 },
4019 /* 818 */
4020 { NACLi_INVALID, 4012 { NACLi_INVALID,
4021 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4013 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4022 InstInvalid, 0x01, 0, 0, 817 }, 4014 InstInvalid, 0x04, 0, 0, 815 },
4015 /* 817 */
4016 { NACLi_SSE2,
4017 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
4018 InstPsrldq, 0x03, 2, 527, 816 },
4019 /* 818 */
4020 { NACLi_SSE2,
4021 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUse sModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_I FLAG(SizeIgnoresData16),
4022 InstPsrlq, 0x02, 2, 527, 817 },
4023 /* 819 */ 4023 /* 819 */
4024 { NACLi_INVALID, 4024 { NACLi_INVALID,
4025 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4025 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4026 InstInvalid, 0x00, 0, 0, 818 }, 4026 InstInvalid, 0x01, 0, 0, 818 },
4027 /* 820 */ 4027 /* 820 */
4028 { NACLi_INVALID,
4029 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4030 InstInvalid, 0x00, 0, 0, 819 },
4031 /* 821 */
4028 { NACLi_SSE2, 4032 { NACLi_SSE2,
4029 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4033 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4030 InstPcmpeqb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4034 InstPcmpeqb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4031 /* 821 */ 4035 /* 822 */
4032 { NACLi_SSE2, 4036 { NACLi_SSE2,
4033 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4037 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4034 InstPcmpeqw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4038 InstPcmpeqw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4035 /* 822 */ 4039 /* 823 */
4036 { NACLi_SSE2, 4040 { NACLi_SSE2,
4037 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4041 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4038 InstPcmpeqd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4042 InstPcmpeqd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4039 /* 823 */ 4043 /* 824 */
4040 { NACLi_INVALID, 4044 { NACLi_INVALID,
4041 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4045 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4042 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 4046 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
4043 /* 824 */ 4047 /* 825 */
4044 { NACLi_SSE4A, 4048 { NACLi_SSE4A,
4045 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeH asImmed_b) | NACL_IFLAG(OpcodeHasImmed2_b) | NACL_IFLAG(OpcodeAllowsData16) | NA CL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4049 NACL_IFLAG(OpcodeInModRm) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeH asImmed_b) | NACL_IFLAG(OpcodeHasImmed2_b) | NACL_IFLAG(OpcodeAllowsData16) | NA CL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4046 InstExtrq, 0x00, 3, 529, 823 }, 4050 InstExtrq, 0x00, 3, 529, 824 },
4047 /* 825 */ 4051 /* 826 */
4048 { NACLi_SSE4A, 4052 { NACLi_SSE4A,
4049 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16), 4053 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16),
4050 InstExtrq, 0x00, 2, 454, NACL_OPCODE_NULL_OFFSET }, 4054 InstExtrq, 0x00, 2, 454, NACL_OPCODE_NULL_OFFSET },
4051 /* 826 */ 4055 /* 827 */
4052 { NACLi_SSE2, 4056 { NACLi_SSE2,
4053 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4057 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4054 InstHaddpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 4058 InstHaddpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
4055 /* 827 */ 4059 /* 828 */
4056 { NACLi_SSE2, 4060 { NACLi_SSE2,
4057 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4061 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4058 InstHsubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 4062 InstHsubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
4059 /* 828 */ 4063 /* 829 */
4060 { NACLi_SSE2, 4064 { NACLi_SSE2,
4061 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_o), 4065 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_o),
4062 InstMovq, 0x00, 2, 532, NACL_OPCODE_NULL_OFFSET }, 4066 InstMovq, 0x00, 2, 532, NACL_OPCODE_NULL_OFFSET },
4063 /* 829 */ 4067 /* 830 */
4064 { NACLi_SSE2, 4068 { NACLi_SSE2,
4065 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_v), 4069 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16) | NACL_IFLAG(OperandSize_v),
4066 InstMovd, 0x00, 2, 534, 828 }, 4070 InstMovd, 0x00, 2, 534, 829 },
4067 /* 830 */ 4071 /* 831 */
4068 { NACLi_SSE2, 4072 { NACLi_SSE2,
4069 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4073 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4070 InstMovdqa, 0x00, 2, 485, NACL_OPCODE_NULL_OFFSET }, 4074 InstMovdqa, 0x00, 2, 485, NACL_OPCODE_NULL_OFFSET },
4071 /* 831 */ 4075 /* 832 */
4072 { NACLi_SSE2, 4076 { NACLi_SSE2,
4073 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4077 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4074 InstCmppd, 0x00, 3, 536, NACL_OPCODE_NULL_OFFSET }, 4078 InstCmppd, 0x00, 3, 536, NACL_OPCODE_NULL_OFFSET },
4075 /* 832 */ 4079 /* 833 */
4076 { NACLi_SSE, 4080 { NACLi_SSE,
4077 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o), 4081 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o),
4078 InstPinsrw, 0x00, 3, 539, NACL_OPCODE_NULL_OFFSET }, 4082 InstPinsrw, 0x00, 3, 539, NACL_OPCODE_NULL_OFFSET },
4079 /* 833 */ 4083 /* 834 */
4080 { NACLi_SSE41, 4084 { NACLi_SSE41,
4081 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeH asImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4085 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeH asImmed_b) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4082 InstPextrw, 0x00, 3, 542, NACL_OPCODE_NULL_OFFSET }, 4086 InstPextrw, 0x00, 3, 542, NACL_OPCODE_NULL_OFFSET },
4083 /* 834 */ 4087 /* 835 */
4084 { NACLi_SSE2, 4088 { NACLi_SSE2,
4085 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4089 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4086 InstShufpd, 0x00, 3, 536, NACL_OPCODE_NULL_OFFSET }, 4090 InstShufpd, 0x00, 3, 536, NACL_OPCODE_NULL_OFFSET },
4087 /* 835 */ 4091 /* 836 */
4088 { NACLi_SSE3, 4092 { NACLi_SSE3,
4089 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4093 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4090 InstAddsubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET }, 4094 InstAddsubpd, 0x00, 2, 459, NACL_OPCODE_NULL_OFFSET },
4091 /* 836 */ 4095 /* 837 */
4092 { NACLi_SSE2, 4096 { NACLi_SSE2,
4093 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4097 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4094 InstPsrlw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4098 InstPsrlw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4095 /* 837 */ 4099 /* 838 */
4096 { NACLi_SSE2, 4100 { NACLi_SSE2,
4097 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4101 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4098 InstPsrld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4102 InstPsrld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4099 /* 838 */ 4103 /* 839 */
4100 { NACLi_SSE2, 4104 { NACLi_SSE2,
4101 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4105 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4102 InstPsrlq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4106 InstPsrlq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4103 /* 839 */ 4107 /* 840 */
4104 { NACLi_SSE2, 4108 { NACLi_SSE2,
4105 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4109 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4106 InstPaddq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4110 InstPaddq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4107 /* 840 */ 4111 /* 841 */
4108 { NACLi_SSE2, 4112 { NACLi_SSE2,
4109 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4113 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4110 InstPmullw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4114 InstPmullw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4111 /* 841 */ 4115 /* 842 */
4112 { NACLi_SSE2, 4116 { NACLi_SSE2,
4113 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4117 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4114 InstMovq, 0x00, 2, 545, NACL_OPCODE_NULL_OFFSET }, 4118 InstMovq, 0x00, 2, 545, NACL_OPCODE_NULL_OFFSET },
4115 /* 842 */ 4119 /* 843 */
4116 { NACLi_SSE2, 4120 { NACLi_SSE2,
4117 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16), 4121 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16),
4118 InstPmovmskb, 0x00, 2, 542, NACL_OPCODE_NULL_OFFSET }, 4122 InstPmovmskb, 0x00, 2, 542, NACL_OPCODE_NULL_OFFSET },
4119 /* 843 */ 4123 /* 844 */
4120 { NACLi_SSE2, 4124 { NACLi_SSE2,
4121 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4125 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4122 InstPsubusb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4126 InstPsubusb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4123 /* 844 */ 4127 /* 845 */
4124 { NACLi_SSE2, 4128 { NACLi_SSE2,
4125 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4129 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4126 InstPsubusw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4130 InstPsubusw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4127 /* 845 */ 4131 /* 846 */
4128 { NACLi_SSE2, 4132 { NACLi_SSE2,
4129 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4133 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4130 InstPminub, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4134 InstPminub, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4131 /* 846 */ 4135 /* 847 */
4132 { NACLi_SSE2, 4136 { NACLi_SSE2,
4133 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4137 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4134 InstPand, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4138 InstPand, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4135 /* 847 */ 4139 /* 848 */
4136 { NACLi_SSE2, 4140 { NACLi_SSE2,
4137 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4141 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4138 InstPaddusb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4142 InstPaddusb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4139 /* 848 */ 4143 /* 849 */
4140 { NACLi_SSE2, 4144 { NACLi_SSE2,
4141 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4145 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4142 InstPaddusw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4146 InstPaddusw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4143 /* 849 */ 4147 /* 850 */
4144 { NACLi_SSE2, 4148 { NACLi_SSE2,
4145 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4149 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4146 InstPmaxub, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4150 InstPmaxub, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4147 /* 850 */ 4151 /* 851 */
4148 { NACLi_SSE2, 4152 { NACLi_SSE2,
4149 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4153 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4150 InstPandn, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4154 InstPandn, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4151 /* 851 */ 4155 /* 852 */
4152 { NACLi_SSE2, 4156 { NACLi_SSE2,
4153 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4157 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4154 InstPavgb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4158 InstPavgb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4155 /* 852 */ 4159 /* 853 */
4156 { NACLi_SSE2, 4160 { NACLi_SSE2,
4157 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4161 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4158 InstPsraw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4162 InstPsraw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4159 /* 853 */ 4163 /* 854 */
4160 { NACLi_SSE2, 4164 { NACLi_SSE2,
4161 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4165 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4162 InstPsrad, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4166 InstPsrad, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4163 /* 854 */ 4167 /* 855 */
4164 { NACLi_SSE2, 4168 { NACLi_SSE2,
4165 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4169 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4166 InstPavgw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4170 InstPavgw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4167 /* 855 */ 4171 /* 856 */
4168 { NACLi_SSE2, 4172 { NACLi_SSE2,
4169 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4173 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4170 InstPmulhuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4174 InstPmulhuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4171 /* 856 */ 4175 /* 857 */
4172 { NACLi_SSE2, 4176 { NACLi_SSE2,
4173 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4177 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4174 InstPmulhw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4178 InstPmulhw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4175 /* 857 */ 4179 /* 858 */
4176 { NACLi_SSE2, 4180 { NACLi_SSE2,
4177 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4181 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4178 InstCvttpd2dq, 0x00, 2, 547, NACL_OPCODE_NULL_OFFSET }, 4182 InstCvttpd2dq, 0x00, 2, 547, NACL_OPCODE_NULL_OFFSET },
4179 /* 858 */ 4183 /* 859 */
4180 { NACLi_SSE2, 4184 { NACLi_SSE2,
4181 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4185 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4182 InstMovntdq, 0x00, 2, 549, NACL_OPCODE_NULL_OFFSET }, 4186 InstMovntdq, 0x00, 2, 549, NACL_OPCODE_NULL_OFFSET },
4183 /* 859 */ 4187 /* 860 */
4184 { NACLi_SSE2, 4188 { NACLi_SSE2,
4185 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4189 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4186 InstPsubsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4190 InstPsubsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4187 /* 860 */ 4191 /* 861 */
4188 { NACLi_SSE2, 4192 { NACLi_SSE2,
4189 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4193 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4190 InstPsubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4194 InstPsubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4191 /* 861 */ 4195 /* 862 */
4192 { NACLi_SSE2, 4196 { NACLi_SSE2,
4193 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4197 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4194 InstPminsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4198 InstPminsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4195 /* 862 */ 4199 /* 863 */
4196 { NACLi_SSE2, 4200 { NACLi_SSE2,
4197 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4201 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4198 InstPor, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4202 InstPor, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4199 /* 863 */ 4203 /* 864 */
4200 { NACLi_SSE2, 4204 { NACLi_SSE2,
4201 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4205 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4202 InstPaddsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4206 InstPaddsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4203 /* 864 */ 4207 /* 865 */
4204 { NACLi_SSE2, 4208 { NACLi_SSE2,
4205 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4209 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4206 InstPaddsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4210 InstPaddsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4207 /* 865 */ 4211 /* 866 */
4208 { NACLi_SSE2, 4212 { NACLi_SSE2,
4209 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4213 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4210 InstPmaxsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4214 InstPmaxsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4211 /* 866 */ 4215 /* 867 */
4212 { NACLi_SSE2, 4216 { NACLi_SSE2,
4213 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4217 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4214 InstPxor, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4218 InstPxor, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4215 /* 867 */ 4219 /* 868 */
4216 { NACLi_SSE2, 4220 { NACLi_SSE2,
4217 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4221 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4218 InstPsllw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4222 InstPsllw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4219 /* 868 */ 4223 /* 869 */
4220 { NACLi_SSE2, 4224 { NACLi_SSE2,
4221 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4225 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4222 InstPslld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4226 InstPslld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4223 /* 869 */ 4227 /* 870 */
4224 { NACLi_SSE2, 4228 { NACLi_SSE2,
4225 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4229 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4226 InstPsllq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4230 InstPsllq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4227 /* 870 */ 4231 /* 871 */
4228 { NACLi_SSE2, 4232 { NACLi_SSE2,
4229 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4233 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4230 InstPmuludq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4234 InstPmuludq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4231 /* 871 */ 4235 /* 872 */
4232 { NACLi_SSE2, 4236 { NACLi_SSE2,
4233 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4237 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4234 InstPmaddwd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4238 InstPmaddwd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4235 /* 872 */ 4239 /* 873 */
4236 { NACLi_SSE2, 4240 { NACLi_SSE2,
4237 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4241 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4238 InstPsadbw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4242 InstPsadbw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4239 /* 873 */ 4243 /* 874 */
4240 { NACLi_SSE2, 4244 { NACLi_SSE2,
4241 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v), 4245 NACL_IFLAG(ModRmModIs0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeA llowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v),
4242 InstMaskmovdqu, 0x00, 3, 551, NACL_OPCODE_NULL_OFFSET }, 4246 InstMaskmovdqu, 0x00, 3, 551, NACL_OPCODE_NULL_OFFSET },
4243 /* 874 */ 4247 /* 875 */
4244 { NACLi_SSE2, 4248 { NACLi_SSE2,
4245 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4249 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4246 InstPsubb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4250 InstPsubb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4247 /* 875 */ 4251 /* 876 */
4248 { NACLi_SSE2, 4252 { NACLi_SSE2,
4249 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4253 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4250 InstPsubw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4254 InstPsubw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4251 /* 876 */ 4255 /* 877 */
4252 { NACLi_SSE2, 4256 { NACLi_SSE2,
4253 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4257 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4254 InstPsubd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4258 InstPsubd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4255 /* 877 */ 4259 /* 878 */
4256 { NACLi_SSE2, 4260 { NACLi_SSE2,
4257 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4261 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4258 InstPsubq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4262 InstPsubq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4259 /* 878 */ 4263 /* 879 */
4260 { NACLi_SSE2, 4264 { NACLi_SSE2,
4261 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4265 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4262 InstPaddb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4266 InstPaddb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4263 /* 879 */ 4267 /* 880 */
4264 { NACLi_SSE2, 4268 { NACLi_SSE2,
4265 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4269 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4266 InstPaddw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4270 InstPaddw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4267 /* 880 */ 4271 /* 881 */
4268 { NACLi_SSE2, 4272 { NACLi_SSE2,
4269 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4273 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4270 InstPaddd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4274 InstPaddd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4271 /* 881 */ 4275 /* 882 */
4272 { NACLi_E3DNOW, 4276 { NACLi_E3DNOW,
4273 NACL_IFLAG(OpcodeUsesModRm), 4277 NACL_IFLAG(OpcodeUsesModRm),
4274 InstPi2fw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4278 InstPi2fw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4275 /* 882 */ 4279 /* 883 */
4276 { NACLi_3DNOW, 4280 { NACLi_3DNOW,
4277 NACL_IFLAG(OpcodeUsesModRm), 4281 NACL_IFLAG(OpcodeUsesModRm),
4278 InstPi2fd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4282 InstPi2fd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4279 /* 883 */ 4283 /* 884 */
4280 { NACLi_E3DNOW, 4284 { NACLi_E3DNOW,
4281 NACL_IFLAG(OpcodeUsesModRm), 4285 NACL_IFLAG(OpcodeUsesModRm),
4282 InstPf2iw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4286 InstPf2iw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4283 /* 884 */ 4287 /* 885 */
4284 { NACLi_3DNOW, 4288 { NACLi_3DNOW,
4285 NACL_IFLAG(OpcodeUsesModRm), 4289 NACL_IFLAG(OpcodeUsesModRm),
4286 InstPf2id, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4290 InstPf2id, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4287 /* 885 */
4288 { NACLi_E3DNOW,
4289 NACL_IFLAG(OpcodeUsesModRm),
4290 InstPfnacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4291 /* 886 */ 4291 /* 886 */
4292 { NACLi_E3DNOW, 4292 { NACLi_E3DNOW,
4293 NACL_IFLAG(OpcodeUsesModRm), 4293 NACL_IFLAG(OpcodeUsesModRm),
4294 InstPfnacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4295 /* 887 */
4296 { NACLi_E3DNOW,
4297 NACL_IFLAG(OpcodeUsesModRm),
4294 InstPfpnacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4298 InstPfpnacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4295 /* 887 */
4296 { NACLi_3DNOW,
4297 NACL_IFLAG(OpcodeUsesModRm),
4298 InstPfcmpge, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4299 /* 888 */ 4299 /* 888 */
4300 { NACLi_3DNOW, 4300 { NACLi_3DNOW,
4301 NACL_IFLAG(OpcodeUsesModRm), 4301 NACL_IFLAG(OpcodeUsesModRm),
4302 InstPfmin, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4302 InstPfcmpge, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4303 /* 889 */ 4303 /* 889 */
4304 { NACLi_3DNOW, 4304 { NACLi_3DNOW,
4305 NACL_IFLAG(OpcodeUsesModRm), 4305 NACL_IFLAG(OpcodeUsesModRm),
4306 InstPfrcp, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4306 InstPfmin, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4307 /* 890 */ 4307 /* 890 */
4308 { NACLi_3DNOW, 4308 { NACLi_3DNOW,
4309 NACL_IFLAG(OpcodeUsesModRm), 4309 NACL_IFLAG(OpcodeUsesModRm),
4310 InstPfrsqrt, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4310 InstPfrcp, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4311 /* 891 */ 4311 /* 891 */
4312 { NACLi_3DNOW, 4312 { NACLi_3DNOW,
4313 NACL_IFLAG(OpcodeUsesModRm), 4313 NACL_IFLAG(OpcodeUsesModRm),
4314 InstPfsub, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4314 InstPfrsqrt, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4315 /* 892 */ 4315 /* 892 */
4316 { NACLi_3DNOW, 4316 { NACLi_3DNOW,
4317 NACL_IFLAG(OpcodeUsesModRm), 4317 NACL_IFLAG(OpcodeUsesModRm),
4318 InstPfadd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4318 InstPfsub, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4319 /* 893 */ 4319 /* 893 */
4320 { NACLi_3DNOW, 4320 { NACLi_3DNOW,
4321 NACL_IFLAG(OpcodeUsesModRm), 4321 NACL_IFLAG(OpcodeUsesModRm),
4322 InstPfcmpgt, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4322 InstPfadd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4323 /* 894 */ 4323 /* 894 */
4324 { NACLi_3DNOW, 4324 { NACLi_3DNOW,
4325 NACL_IFLAG(OpcodeUsesModRm), 4325 NACL_IFLAG(OpcodeUsesModRm),
4326 InstPfmax, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4326 InstPfcmpgt, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4327 /* 895 */ 4327 /* 895 */
4328 { NACLi_3DNOW, 4328 { NACLi_3DNOW,
4329 NACL_IFLAG(OpcodeUsesModRm), 4329 NACL_IFLAG(OpcodeUsesModRm),
4330 InstPfrcpit1, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4330 InstPfmax, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4331 /* 896 */ 4331 /* 896 */
4332 { NACLi_3DNOW, 4332 { NACLi_3DNOW,
4333 NACL_IFLAG(OpcodeUsesModRm), 4333 NACL_IFLAG(OpcodeUsesModRm),
4334 InstPfrsqit1, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4334 InstPfrcpit1, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4335 /* 897 */ 4335 /* 897 */
4336 { NACLi_3DNOW, 4336 { NACLi_3DNOW,
4337 NACL_IFLAG(OpcodeUsesModRm), 4337 NACL_IFLAG(OpcodeUsesModRm),
4338 InstPfsubr, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4338 InstPfrsqit1, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4339 /* 898 */ 4339 /* 898 */
4340 { NACLi_3DNOW, 4340 { NACLi_3DNOW,
4341 NACL_IFLAG(OpcodeUsesModRm), 4341 NACL_IFLAG(OpcodeUsesModRm),
4342 InstPfacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4342 InstPfsubr, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4343 /* 899 */ 4343 /* 899 */
4344 { NACLi_3DNOW, 4344 { NACLi_3DNOW,
4345 NACL_IFLAG(OpcodeUsesModRm), 4345 NACL_IFLAG(OpcodeUsesModRm),
4346 InstPfcmpeq, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4346 InstPfacc, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4347 /* 900 */ 4347 /* 900 */
4348 { NACLi_3DNOW, 4348 { NACLi_3DNOW,
4349 NACL_IFLAG(OpcodeUsesModRm), 4349 NACL_IFLAG(OpcodeUsesModRm),
4350 InstPfmul, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4350 InstPfcmpeq, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4351 /* 901 */ 4351 /* 901 */
4352 { NACLi_3DNOW, 4352 { NACLi_3DNOW,
4353 NACL_IFLAG(OpcodeUsesModRm), 4353 NACL_IFLAG(OpcodeUsesModRm),
4354 InstPfrcpit2, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4354 InstPfmul, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4355 /* 902 */ 4355 /* 902 */
4356 { NACLi_3DNOW, 4356 { NACLi_3DNOW,
4357 NACL_IFLAG(OpcodeUsesModRm), 4357 NACL_IFLAG(OpcodeUsesModRm),
4358 InstPfrcpit2, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4359 /* 903 */
4360 { NACLi_3DNOW,
4361 NACL_IFLAG(OpcodeUsesModRm),
4358 InstPmulhrw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4362 InstPmulhrw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4359 /* 903 */ 4363 /* 904 */
4360 { NACLi_E3DNOW, 4364 { NACLi_E3DNOW,
4361 NACL_IFLAG(OpcodeUsesModRm), 4365 NACL_IFLAG(OpcodeUsesModRm),
4362 InstPswapd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4366 InstPswapd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4363 /* 904 */ 4367 /* 905 */
4364 { NACLi_3DNOW, 4368 { NACLi_3DNOW,
4365 NACL_IFLAG(OpcodeUsesModRm), 4369 NACL_IFLAG(OpcodeUsesModRm),
4366 InstPavgusb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4370 InstPavgusb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4367 /* 905 */ 4371 /* 906 */
4368 { NACLi_SSSE3, 4372 { NACLi_SSSE3,
4369 NACL_IFLAG(OpcodeUsesModRm), 4373 NACL_IFLAG(OpcodeUsesModRm),
4370 InstPshufb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4374 InstPshufb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4371 /* 906 */ 4375 /* 907 */
4372 { NACLi_SSSE3, 4376 { NACLi_SSSE3,
4373 NACL_IFLAG(OpcodeUsesModRm), 4377 NACL_IFLAG(OpcodeUsesModRm),
4374 InstPhaddw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4378 InstPhaddw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4375 /* 907 */ 4379 /* 908 */
4376 { NACLi_SSSE3, 4380 { NACLi_SSSE3,
4377 NACL_IFLAG(OpcodeUsesModRm), 4381 NACL_IFLAG(OpcodeUsesModRm),
4378 InstPhaddd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4382 InstPhaddd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4379 /* 908 */ 4383 /* 909 */
4380 { NACLi_SSSE3, 4384 { NACLi_SSSE3,
4381 NACL_IFLAG(OpcodeUsesModRm), 4385 NACL_IFLAG(OpcodeUsesModRm),
4382 InstPhaddsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4386 InstPhaddsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4383 /* 909 */ 4387 /* 910 */
4384 { NACLi_SSSE3, 4388 { NACLi_SSSE3,
4385 NACL_IFLAG(OpcodeUsesModRm), 4389 NACL_IFLAG(OpcodeUsesModRm),
4386 InstPmaddubsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4390 InstPmaddubsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4387 /* 910 */ 4391 /* 911 */
4388 { NACLi_SSSE3, 4392 { NACLi_SSSE3,
4389 NACL_IFLAG(OpcodeUsesModRm), 4393 NACL_IFLAG(OpcodeUsesModRm),
4390 InstPhsubw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4394 InstPhsubw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4391 /* 911 */ 4395 /* 912 */
4392 { NACLi_SSSE3, 4396 { NACLi_SSSE3,
4393 NACL_IFLAG(OpcodeUsesModRm), 4397 NACL_IFLAG(OpcodeUsesModRm),
4394 InstPhsubd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4398 InstPhsubd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4395 /* 912 */ 4399 /* 913 */
4396 { NACLi_SSSE3, 4400 { NACLi_SSSE3,
4397 NACL_IFLAG(OpcodeUsesModRm), 4401 NACL_IFLAG(OpcodeUsesModRm),
4398 InstPhsubsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4402 InstPhsubsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4399 /* 913 */ 4403 /* 914 */
4400 { NACLi_SSSE3, 4404 { NACLi_SSSE3,
4401 NACL_IFLAG(OpcodeUsesModRm), 4405 NACL_IFLAG(OpcodeUsesModRm),
4402 InstPsignb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4406 InstPsignb, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4403 /* 914 */ 4407 /* 915 */
4404 { NACLi_SSSE3, 4408 { NACLi_SSSE3,
4405 NACL_IFLAG(OpcodeUsesModRm), 4409 NACL_IFLAG(OpcodeUsesModRm),
4406 InstPsignw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4410 InstPsignw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4407 /* 915 */ 4411 /* 916 */
4408 { NACLi_SSSE3, 4412 { NACLi_SSSE3,
4409 NACL_IFLAG(OpcodeUsesModRm), 4413 NACL_IFLAG(OpcodeUsesModRm),
4410 InstPsignd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4414 InstPsignd, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4411 /* 916 */ 4415 /* 917 */
4412 { NACLi_SSSE3, 4416 { NACLi_SSSE3,
4413 NACL_IFLAG(OpcodeUsesModRm), 4417 NACL_IFLAG(OpcodeUsesModRm),
4414 InstPmulhrsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET }, 4418 InstPmulhrsw, 0x00, 2, 350, NACL_OPCODE_NULL_OFFSET },
4415 /* 917 */ 4419 /* 918 */
4416 { NACLi_SSSE3, 4420 { NACLi_SSSE3,
4417 NACL_IFLAG(OpcodeUsesModRm), 4421 NACL_IFLAG(OpcodeUsesModRm),
4418 InstPabsb, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4422 InstPabsb, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4419 /* 918 */ 4423 /* 919 */
4420 { NACLi_SSSE3, 4424 { NACLi_SSSE3,
4421 NACL_IFLAG(OpcodeUsesModRm), 4425 NACL_IFLAG(OpcodeUsesModRm),
4422 InstPabsw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4426 InstPabsw, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4423 /* 919 */ 4427 /* 920 */
4424 { NACLi_SSSE3, 4428 { NACLi_SSSE3,
4425 NACL_IFLAG(OpcodeUsesModRm), 4429 NACL_IFLAG(OpcodeUsesModRm),
4426 InstPabsd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET }, 4430 InstPabsd, 0x00, 2, 358, NACL_OPCODE_NULL_OFFSET },
4427 /* 920 */ 4431 /* 921 */
4428 { NACLi_MOVBE, 4432 { NACLi_MOVBE,
4429 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o), 4433 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o),
4430 InstMovbe, 0x00, 2, 554, NACL_OPCODE_NULL_OFFSET }, 4434 InstMovbe, 0x00, 2, 554, NACL_OPCODE_NULL_OFFSET },
4431 /* 921 */ 4435 /* 922 */
4432 { NACLi_MOVBE, 4436 { NACLi_MOVBE,
4433 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o), 4437 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_IF LAG(OperandSize_o),
4434 InstMovbe, 0x00, 2, 556, NACL_OPCODE_NULL_OFFSET }, 4438 InstMovbe, 0x00, 2, 556, NACL_OPCODE_NULL_OFFSET },
4435 /* 922 */ 4439 /* 923 */
4436 { NACLi_SSSE3, 4440 { NACLi_SSSE3,
4437 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4441 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4438 InstPshufb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4442 InstPshufb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4439 /* 923 */ 4443 /* 924 */
4440 { NACLi_SSSE3, 4444 { NACLi_SSSE3,
4441 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4445 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4442 InstPhaddw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4446 InstPhaddw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4443 /* 924 */ 4447 /* 925 */
4444 { NACLi_SSSE3, 4448 { NACLi_SSSE3,
4445 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4449 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4446 InstPhaddd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4450 InstPhaddd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4447 /* 925 */ 4451 /* 926 */
4448 { NACLi_SSSE3, 4452 { NACLi_SSSE3,
4449 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4453 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4450 InstPhaddsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4454 InstPhaddsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4451 /* 926 */ 4455 /* 927 */
4452 { NACLi_SSSE3, 4456 { NACLi_SSSE3,
4453 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4457 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4454 InstPmaddubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4458 InstPmaddubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4455 /* 927 */ 4459 /* 928 */
4456 { NACLi_SSSE3, 4460 { NACLi_SSSE3,
4457 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4461 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4458 InstPhsubw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4462 InstPhsubw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4459 /* 928 */ 4463 /* 929 */
4460 { NACLi_SSSE3, 4464 { NACLi_SSSE3,
4461 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4465 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4462 InstPhsubd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4466 InstPhsubd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4463 /* 929 */ 4467 /* 930 */
4464 { NACLi_SSSE3, 4468 { NACLi_SSSE3,
4465 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4469 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4466 InstPhsubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4470 InstPhsubsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4467 /* 930 */ 4471 /* 931 */
4468 { NACLi_SSSE3, 4472 { NACLi_SSSE3,
4469 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4473 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4470 InstPsignb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4474 InstPsignb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4471 /* 931 */ 4475 /* 932 */
4472 { NACLi_SSSE3, 4476 { NACLi_SSSE3,
4473 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4477 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4474 InstPsignw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4478 InstPsignw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4475 /* 932 */ 4479 /* 933 */
4476 { NACLi_SSSE3, 4480 { NACLi_SSSE3,
4477 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4481 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4478 InstPsignd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4482 InstPsignd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4479 /* 933 */ 4483 /* 934 */
4480 { NACLi_SSSE3, 4484 { NACLi_SSSE3,
4481 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4485 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4482 InstPmulhrsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4486 InstPmulhrsw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4483 /* 934 */ 4487 /* 935 */
4484 { NACLi_SSE41, 4488 { NACLi_SSE41,
4485 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4489 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4486 InstPblendvb, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET }, 4490 InstPblendvb, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET },
4487 /* 935 */ 4491 /* 936 */
4488 { NACLi_SSE41, 4492 { NACLi_SSE41,
4489 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4493 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4490 InstBlendvps, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET }, 4494 InstBlendvps, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET },
4491 /* 936 */ 4495 /* 937 */
4492 { NACLi_SSE41, 4496 { NACLi_SSE41,
4493 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4497 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4494 InstBlendvpd, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET }, 4498 InstBlendvpd, 0x00, 3, 558, NACL_OPCODE_NULL_OFFSET },
4495 /* 937 */ 4499 /* 938 */
4496 { NACLi_SSE41, 4500 { NACLi_SSE41,
4497 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4501 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4498 InstPtest, 0x00, 2, 561, NACL_OPCODE_NULL_OFFSET }, 4502 InstPtest, 0x00, 2, 561, NACL_OPCODE_NULL_OFFSET },
4499 /* 938 */ 4503 /* 939 */
4500 { NACLi_SSSE3, 4504 { NACLi_SSSE3,
4501 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4505 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4502 InstPabsb, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET }, 4506 InstPabsb, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET },
4503 /* 939 */ 4507 /* 940 */
4504 { NACLi_SSSE3, 4508 { NACLi_SSSE3,
4505 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4509 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4506 InstPabsw, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET }, 4510 InstPabsw, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET },
4507 /* 940 */ 4511 /* 941 */
4508 { NACLi_SSSE3, 4512 { NACLi_SSSE3,
4509 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4513 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4510 InstPabsd, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET }, 4514 InstPabsd, 0x00, 2, 483, NACL_OPCODE_NULL_OFFSET },
4511 /* 941 */ 4515 /* 942 */
4512 { NACLi_SSE41, 4516 { NACLi_SSE41,
4513 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4517 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4514 InstPmovsxbw, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4518 InstPmovsxbw, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4515 /* 942 */ 4519 /* 943 */
4516 { NACLi_SSE41, 4520 { NACLi_SSE41,
4517 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4521 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4518 InstPmovsxbd, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET }, 4522 InstPmovsxbd, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET },
4519 /* 943 */ 4523 /* 944 */
4520 { NACLi_SSE41, 4524 { NACLi_SSE41,
4521 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4525 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4522 InstPmovsxbq, 0x00, 2, 567, NACL_OPCODE_NULL_OFFSET }, 4526 InstPmovsxbq, 0x00, 2, 567, NACL_OPCODE_NULL_OFFSET },
4523 /* 944 */ 4527 /* 945 */
4524 { NACLi_SSE41, 4528 { NACLi_SSE41,
4525 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4529 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4526 InstPmovsxwd, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4530 InstPmovsxwd, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4527 /* 945 */ 4531 /* 946 */
4528 { NACLi_SSE41, 4532 { NACLi_SSE41,
4529 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4533 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4530 InstPmovsxwq, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET }, 4534 InstPmovsxwq, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET },
4531 /* 946 */ 4535 /* 947 */
4532 { NACLi_SSE41, 4536 { NACLi_SSE41,
4533 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4537 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4534 InstPmovsxdq, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4538 InstPmovsxdq, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4535 /* 947 */ 4539 /* 948 */
4536 { NACLi_SSE41, 4540 { NACLi_SSE41,
4537 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4541 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4538 InstPmuldq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4542 InstPmuldq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4539 /* 948 */ 4543 /* 949 */
4540 { NACLi_SSE41, 4544 { NACLi_SSE41,
4541 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4545 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4542 InstPcmpeqq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4546 InstPcmpeqq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4543 /* 949 */ 4547 /* 950 */
4544 { NACLi_SSE41, 4548 { NACLi_SSE41,
4545 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4549 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4546 InstMovntdqa, 0x00, 2, 465, NACL_OPCODE_NULL_OFFSET }, 4550 InstMovntdqa, 0x00, 2, 465, NACL_OPCODE_NULL_OFFSET },
4547 /* 950 */ 4551 /* 951 */
4548 { NACLi_SSE41, 4552 { NACLi_SSE41,
4549 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4553 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4550 InstPackusdw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4554 InstPackusdw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4551 /* 951 */ 4555 /* 952 */
4552 { NACLi_SSE41, 4556 { NACLi_SSE41,
4553 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4557 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4554 InstPmovzxbw, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4558 InstPmovzxbw, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4555 /* 952 */ 4559 /* 953 */
4556 { NACLi_SSE41, 4560 { NACLi_SSE41,
4557 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4561 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4558 InstPmovzxbd, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET }, 4562 InstPmovzxbd, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET },
4559 /* 953 */ 4563 /* 954 */
4560 { NACLi_SSE41, 4564 { NACLi_SSE41,
4561 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4565 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4562 InstPmovzxbq, 0x00, 2, 567, NACL_OPCODE_NULL_OFFSET }, 4566 InstPmovzxbq, 0x00, 2, 567, NACL_OPCODE_NULL_OFFSET },
4563 /* 954 */ 4567 /* 955 */
4564 { NACLi_SSE41, 4568 { NACLi_SSE41,
4565 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4569 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4566 InstPmovzxwd, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4570 InstPmovzxwd, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4567 /* 955 */ 4571 /* 956 */
4568 { NACLi_SSE41, 4572 { NACLi_SSE41,
4569 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4573 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4570 InstPmovzxwq, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET }, 4574 InstPmovzxwq, 0x00, 2, 565, NACL_OPCODE_NULL_OFFSET },
4571 /* 956 */ 4575 /* 957 */
4572 { NACLi_SSE41, 4576 { NACLi_SSE41,
4573 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4577 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4574 InstPmovzxdq, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET }, 4578 InstPmovzxdq, 0x00, 2, 563, NACL_OPCODE_NULL_OFFSET },
4575 /* 957 */ 4579 /* 958 */
4576 { NACLi_SSE42, 4580 { NACLi_SSE42,
4577 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4581 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4578 InstPcmpgtq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4582 InstPcmpgtq, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4579 /* 958 */ 4583 /* 959 */
4580 { NACLi_SSE41, 4584 { NACLi_SSE41,
4581 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4585 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4582 InstPminsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4586 InstPminsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4583 /* 959 */ 4587 /* 960 */
4584 { NACLi_SSE41, 4588 { NACLi_SSE41,
4585 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4589 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4586 InstPminsd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4590 InstPminsd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4587 /* 960 */ 4591 /* 961 */
4588 { NACLi_SSE41, 4592 { NACLi_SSE41,
4589 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4593 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4590 InstPminuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4594 InstPminuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4591 /* 961 */ 4595 /* 962 */
4592 { NACLi_SSE41, 4596 { NACLi_SSE41,
4593 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4597 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4594 InstPminud, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4598 InstPminud, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4595 /* 962 */ 4599 /* 963 */
4596 { NACLi_SSE41, 4600 { NACLi_SSE41,
4597 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4601 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4598 InstPmaxsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4602 InstPmaxsb, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4599 /* 963 */ 4603 /* 964 */
4600 { NACLi_SSE41, 4604 { NACLi_SSE41,
4601 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4605 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4602 InstPmaxsd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4606 InstPmaxsd, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4603 /* 964 */ 4607 /* 965 */
4604 { NACLi_SSE41, 4608 { NACLi_SSE41,
4605 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4609 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4606 InstPmaxuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4610 InstPmaxuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4607 /* 965 */ 4611 /* 966 */
4608 { NACLi_SSE41, 4612 { NACLi_SSE41,
4609 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4613 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4610 InstPmaxud, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4614 InstPmaxud, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4611 /* 966 */ 4615 /* 967 */
4612 { NACLi_SSE41, 4616 { NACLi_SSE41,
4613 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4617 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4614 InstPmulld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4618 InstPmulld, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4615 /* 967 */ 4619 /* 968 */
4616 { NACLi_SSE41, 4620 { NACLi_SSE41,
4617 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16), 4621 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsData16) | NACL_IFLAG(Si zeIgnoresData16),
4618 InstPhminposuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET }, 4622 InstPhminposuw, 0x00, 2, 518, NACL_OPCODE_NULL_OFFSET },
4619 /* 968 */ 4623 /* 969 */
4620 { NACLi_VMX, 4624 { NACLi_VMX,
4621 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4625 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4622 InstInvept, 0x00, 2, 569, NACL_OPCODE_NULL_OFFSET }, 4626 InstInvept, 0x00, 2, 569, NACL_OPCODE_NULL_OFFSET },
4623 /* 969 */ 4627 /* 970 */
4624 { NACLi_VMX, 4628 { NACLi_VMX,
4625 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal), 4629 NACL_IFLAG(ModRmModIsnt0x3) | NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(Opcod eAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(NaClIllegal),
4626 InstInvvpid, 0x00, 2, 569, NACL_OPCODE_NULL_OFFSET }, 4630 InstInvvpid, 0x00, 2, 569, NACL_OPCODE_NULL_OFFSET },
4627 /* 970 */ 4631 /* 971 */
4628 { NACLi_SSE42, 4632 { NACLi_SSE42,
4629 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRepne) | NACL_IFLAG(Ope randSize_b), 4633 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRepne) | NACL_IFLAG(Ope randSize_b),
4630 InstCrc32, 0x00, 2, 571, NACL_OPCODE_NULL_OFFSET }, 4634 InstCrc32, 0x00, 2, 571, NACL_OPCODE_NULL_OFFSET },
4631 /* 971 */ 4635 /* 972 */
4632 { NACLi_SSE42, 4636 { NACLi_SSE42,
4633 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRepne) | NACL_IFLAG(Opc odeAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_ IFLAG(OperandSize_o), 4637 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeAllowsRepne) | NACL_IFLAG(Opc odeAllowsData16) | NACL_IFLAG(OperandSize_w) | NACL_IFLAG(OperandSize_v) | NACL_ IFLAG(OperandSize_o),
4634 InstCrc32, 0x00, 2, 573, NACL_OPCODE_NULL_OFFSET }, 4638 InstCrc32, 0x00, 2, 573, NACL_OPCODE_NULL_OFFSET },
4635 /* 972 */ 4639 /* 973 */
4636 { NACLi_SSSE3, 4640 { NACLi_SSSE3,
4637 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b), 4641 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b),
4638 InstPalignr, 0x00, 3, 575, NACL_OPCODE_NULL_OFFSET }, 4642 InstPalignr, 0x00, 3, 575, NACL_OPCODE_NULL_OFFSET },
4639 /* 973 */ 4643 /* 974 */
4640 { NACLi_SSE41, 4644 { NACLi_SSE41,
4641 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4645 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4642 InstRoundps, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET }, 4646 InstRoundps, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET },
4643 /* 974 */ 4647 /* 975 */
4644 { NACLi_SSE41, 4648 { NACLi_SSE41,
4645 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4649 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4646 InstRoundpd, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET }, 4650 InstRoundpd, 0x00, 3, 524, NACL_OPCODE_NULL_OFFSET },
4647 /* 975 */ 4651 /* 976 */
4648 { NACLi_SSE41, 4652 { NACLi_SSE41,
4649 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4653 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4650 InstRoundss, 0x00, 3, 578, NACL_OPCODE_NULL_OFFSET }, 4654 InstRoundss, 0x00, 3, 578, NACL_OPCODE_NULL_OFFSET },
4651 /* 976 */ 4655 /* 977 */
4652 { NACLi_SSE41, 4656 { NACLi_SSE41,
4653 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4657 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4654 InstRoundsd, 0x00, 3, 581, NACL_OPCODE_NULL_OFFSET }, 4658 InstRoundsd, 0x00, 3, 581, NACL_OPCODE_NULL_OFFSET },
4655 /* 977 */ 4659 /* 978 */
4656 { NACLi_SSE41, 4660 { NACLi_SSE41,
4657 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4661 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4658 InstBlendps, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4662 InstBlendps, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4659 /* 978 */ 4663 /* 979 */
4660 { NACLi_SSE41, 4664 { NACLi_SSE41,
4661 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4665 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4662 InstBlendpd, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4666 InstBlendpd, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4663 /* 979 */ 4667 /* 980 */
4664 { NACLi_SSE41, 4668 { NACLi_SSE41,
4665 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4669 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4666 InstPblendw, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4670 InstPblendw, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4667 /* 980 */ 4671 /* 981 */
4668 { NACLi_SSSE3, 4672 { NACLi_SSSE3,
4669 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4673 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4670 InstPalignr, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4674 InstPalignr, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4671 /* 981 */ 4675 /* 982 */
4672 { NACLi_SSE41, 4676 { NACLi_SSE41,
4673 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4677 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4674 InstPextrb, 0x00, 3, 587, NACL_OPCODE_NULL_OFFSET }, 4678 InstPextrb, 0x00, 3, 587, NACL_OPCODE_NULL_OFFSET },
4675 /* 982 */ 4679 /* 983 */
4676 { NACLi_SSE41, 4680 { NACLi_SSE41,
4677 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4681 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4678 InstPextrw, 0x00, 3, 590, NACL_OPCODE_NULL_OFFSET }, 4682 InstPextrw, 0x00, 3, 590, NACL_OPCODE_NULL_OFFSET },
4679 /* 983 */ 4683 /* 984 */
4680 { NACLi_SSE41, 4684 { NACLi_SSE41,
4681 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_o), 4685 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_o),
4682 InstPextrq, 0x00, 3, 593, NACL_OPCODE_NULL_OFFSET }, 4686 InstPextrq, 0x00, 3, 593, NACL_OPCODE_NULL_OFFSET },
4683 /* 984 */ 4687 /* 985 */
4684 { NACLi_SSE41, 4688 { NACLi_SSE41,
4685 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v), 4689 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v),
4686 InstPextrd, 0x00, 3, 596, 983 }, 4690 InstPextrd, 0x00, 3, 596, 984 },
4687 /* 985 */ 4691 /* 986 */
4688 { NACLi_SSE41, 4692 { NACLi_SSE41,
4689 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4693 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4690 InstExtractps, 0x00, 3, 599, NACL_OPCODE_NULL_OFFSET }, 4694 InstExtractps, 0x00, 3, 599, NACL_OPCODE_NULL_OFFSET },
4691 /* 986 */ 4695 /* 987 */
4692 { NACLi_SSE41, 4696 { NACLi_SSE41,
4693 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o), 4697 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o),
4694 InstPinsrb, 0x00, 3, 602, NACL_OPCODE_NULL_OFFSET }, 4698 InstPinsrb, 0x00, 3, 602, NACL_OPCODE_NULL_OFFSET },
4695 /* 987 */ 4699 /* 988 */
4696 { NACLi_SSE41, 4700 { NACLi_SSE41,
4697 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4701 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4698 InstInsertps, 0x00, 3, 605, NACL_OPCODE_NULL_OFFSET }, 4702 InstInsertps, 0x00, 3, 605, NACL_OPCODE_NULL_OFFSET },
4699 /* 988 */ 4703 /* 989 */
4700 { NACLi_SSE41, 4704 { NACLi_SSE41,
4701 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_o), 4705 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_o),
4702 InstPinsrq, 0x00, 3, 608, NACL_OPCODE_NULL_OFFSET }, 4706 InstPinsrq, 0x00, 3, 608, NACL_OPCODE_NULL_OFFSET },
4703 /* 989 */ 4707 /* 990 */
4704 { NACLi_SSE41, 4708 { NACLi_SSE41,
4705 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v), 4709 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v),
4706 InstPinsrd, 0x00, 3, 611, 988 }, 4710 InstPinsrd, 0x00, 3, 611, 989 },
4707 /* 990 */ 4711 /* 991 */
4708 { NACLi_SSE41, 4712 { NACLi_SSE41,
4709 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4713 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4710 InstDpps, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4714 InstDpps, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4711 /* 991 */ 4715 /* 992 */
4712 { NACLi_SSE41, 4716 { NACLi_SSE41,
4713 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4717 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4714 InstDppd, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4718 InstDppd, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4715 /* 992 */ 4719 /* 993 */
4716 { NACLi_SSE41, 4720 { NACLi_SSE41,
4717 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4721 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4718 InstMpsadbw, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET }, 4722 InstMpsadbw, 0x00, 3, 584, NACL_OPCODE_NULL_OFFSET },
4719 /* 993 */ 4723 /* 994 */
4720 { NACLi_SSE42, 4724 { NACLi_SSE42,
4721 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o), 4725 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o),
4722 InstPcmpestrm, 0x00, 6, 614, NACL_OPCODE_NULL_OFFSET }, 4726 InstPcmpestrm, 0x00, 6, 614, NACL_OPCODE_NULL_OFFSET },
4723 /* 994 */ 4727 /* 995 */
4724 { NACLi_SSE42, 4728 { NACLi_SSE42,
4725 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o), 4729 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o),
4726 InstPcmpestri, 0x00, 6, 620, NACL_OPCODE_NULL_OFFSET }, 4730 InstPcmpestri, 0x00, 6, 620, NACL_OPCODE_NULL_OFFSET },
4727 /* 995 */ 4731 /* 996 */
4728 { NACLi_SSE42, 4732 { NACLi_SSE42,
4729 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16), 4733 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16),
4730 InstPcmpistrm, 0x00, 4, 626, NACL_OPCODE_NULL_OFFSET }, 4734 InstPcmpistrm, 0x00, 4, 626, NACL_OPCODE_NULL_OFFSET },
4731 /* 996 */ 4735 /* 997 */
4732 { NACLi_SSE42, 4736 { NACLi_SSE42,
4733 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o), 4737 NACL_IFLAG(OpcodeUsesModRm) | NACL_IFLAG(OpcodeHasImmed_b) | NACL_IFLAG(Opco deAllowsData16) | NACL_IFLAG(SizeIgnoresData16) | NACL_IFLAG(OperandSize_v) | NA CL_IFLAG(OperandSize_o),
4734 InstPcmpistri, 0x00, 4, 630, NACL_OPCODE_NULL_OFFSET }, 4738 InstPcmpistri, 0x00, 4, 630, NACL_OPCODE_NULL_OFFSET },
4735 /* 997 */ 4739 /* 998 */
4736 { NACLi_X87, 4740 { NACLi_X87,
4737 NACL_EMPTY_IFLAGS, 4741 NACL_EMPTY_IFLAGS,
4738 InstFadd, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4742 InstFadd, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4739 /* 998 */ 4743 /* 999 */
4740 { NACLi_X87, 4744 { NACLi_X87,
4741 NACL_EMPTY_IFLAGS, 4745 NACL_EMPTY_IFLAGS,
4742 InstFadd, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4746 InstFadd, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4743 /* 999 */ 4747 /* 1000 */
4744 { NACLi_X87, 4748 { NACLi_X87,
4745 NACL_EMPTY_IFLAGS, 4749 NACL_EMPTY_IFLAGS,
4746 InstFadd, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4750 InstFadd, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4747 /* 1000 */ 4751 /* 1001 */
4748 { NACLi_X87, 4752 { NACLi_X87,
4749 NACL_EMPTY_IFLAGS, 4753 NACL_EMPTY_IFLAGS,
4750 InstFadd, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4754 InstFadd, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4751 /* 1001 */ 4755 /* 1002 */
4752 { NACLi_X87, 4756 { NACLi_X87,
4753 NACL_EMPTY_IFLAGS, 4757 NACL_EMPTY_IFLAGS,
4754 InstFadd, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4758 InstFadd, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4755 /* 1002 */ 4759 /* 1003 */
4756 { NACLi_X87, 4760 { NACLi_X87,
4757 NACL_EMPTY_IFLAGS, 4761 NACL_EMPTY_IFLAGS,
4758 InstFadd, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4762 InstFadd, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4759 /* 1003 */ 4763 /* 1004 */
4760 { NACLi_X87, 4764 { NACLi_X87,
4761 NACL_EMPTY_IFLAGS, 4765 NACL_EMPTY_IFLAGS,
4762 InstFadd, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4766 InstFadd, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4763 /* 1004 */ 4767 /* 1005 */
4764 { NACLi_X87, 4768 { NACLi_X87,
4765 NACL_EMPTY_IFLAGS, 4769 NACL_EMPTY_IFLAGS,
4766 InstFadd, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4770 InstFadd, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4767 /* 1005 */ 4771 /* 1006 */
4768 { NACLi_X87, 4772 { NACLi_X87,
4769 NACL_EMPTY_IFLAGS, 4773 NACL_EMPTY_IFLAGS,
4770 InstFmul, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4774 InstFmul, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4771 /* 1006 */ 4775 /* 1007 */
4772 { NACLi_X87, 4776 { NACLi_X87,
4773 NACL_EMPTY_IFLAGS, 4777 NACL_EMPTY_IFLAGS,
4774 InstFmul, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4778 InstFmul, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4775 /* 1007 */ 4779 /* 1008 */
4776 { NACLi_X87, 4780 { NACLi_X87,
4777 NACL_EMPTY_IFLAGS, 4781 NACL_EMPTY_IFLAGS,
4778 InstFmul, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4782 InstFmul, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4779 /* 1008 */ 4783 /* 1009 */
4780 { NACLi_X87, 4784 { NACLi_X87,
4781 NACL_EMPTY_IFLAGS, 4785 NACL_EMPTY_IFLAGS,
4782 InstFmul, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4786 InstFmul, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4783 /* 1009 */ 4787 /* 1010 */
4784 { NACLi_X87, 4788 { NACLi_X87,
4785 NACL_EMPTY_IFLAGS, 4789 NACL_EMPTY_IFLAGS,
4786 InstFmul, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4790 InstFmul, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4787 /* 1010 */ 4791 /* 1011 */
4788 { NACLi_X87, 4792 { NACLi_X87,
4789 NACL_EMPTY_IFLAGS, 4793 NACL_EMPTY_IFLAGS,
4790 InstFmul, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4794 InstFmul, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4791 /* 1011 */ 4795 /* 1012 */
4792 { NACLi_X87, 4796 { NACLi_X87,
4793 NACL_EMPTY_IFLAGS, 4797 NACL_EMPTY_IFLAGS,
4794 InstFmul, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4798 InstFmul, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4795 /* 1012 */ 4799 /* 1013 */
4796 { NACLi_X87, 4800 { NACLi_X87,
4797 NACL_EMPTY_IFLAGS, 4801 NACL_EMPTY_IFLAGS,
4798 InstFmul, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4802 InstFmul, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4799 /* 1013 */ 4803 /* 1014 */
4800 { NACLi_X87, 4804 { NACLi_X87,
4801 NACL_EMPTY_IFLAGS, 4805 NACL_EMPTY_IFLAGS,
4802 InstFcom, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 4806 InstFcom, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
4803 /* 1014 */ 4807 /* 1015 */
4804 { NACLi_X87, 4808 { NACLi_X87,
4805 NACL_EMPTY_IFLAGS, 4809 NACL_EMPTY_IFLAGS,
4806 InstFcom, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 4810 InstFcom, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
4807 /* 1015 */ 4811 /* 1016 */
4808 { NACLi_X87, 4812 { NACLi_X87,
4809 NACL_EMPTY_IFLAGS, 4813 NACL_EMPTY_IFLAGS,
4810 InstFcom, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 4814 InstFcom, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
4811 /* 1016 */ 4815 /* 1017 */
4812 { NACLi_X87, 4816 { NACLi_X87,
4813 NACL_EMPTY_IFLAGS, 4817 NACL_EMPTY_IFLAGS,
4814 InstFcom, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 4818 InstFcom, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
4815 /* 1017 */ 4819 /* 1018 */
4816 { NACLi_X87, 4820 { NACLi_X87,
4817 NACL_EMPTY_IFLAGS, 4821 NACL_EMPTY_IFLAGS,
4818 InstFcom, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 4822 InstFcom, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
4819 /* 1018 */ 4823 /* 1019 */
4820 { NACLi_X87, 4824 { NACLi_X87,
4821 NACL_EMPTY_IFLAGS, 4825 NACL_EMPTY_IFLAGS,
4822 InstFcom, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 4826 InstFcom, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
4823 /* 1019 */ 4827 /* 1020 */
4824 { NACLi_X87, 4828 { NACLi_X87,
4825 NACL_EMPTY_IFLAGS, 4829 NACL_EMPTY_IFLAGS,
4826 InstFcom, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 4830 InstFcom, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
4827 /* 1020 */ 4831 /* 1021 */
4828 { NACLi_X87, 4832 { NACLi_X87,
4829 NACL_EMPTY_IFLAGS, 4833 NACL_EMPTY_IFLAGS,
4830 InstFcom, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 4834 InstFcom, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
4831 /* 1021 */ 4835 /* 1022 */
4832 { NACLi_X87, 4836 { NACLi_X87,
4833 NACL_EMPTY_IFLAGS, 4837 NACL_EMPTY_IFLAGS,
4834 InstFcomp, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 4838 InstFcomp, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
4835 /* 1022 */ 4839 /* 1023 */
4836 { NACLi_X87, 4840 { NACLi_X87,
4837 NACL_EMPTY_IFLAGS, 4841 NACL_EMPTY_IFLAGS,
4838 InstFcomp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 4842 InstFcomp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
4839 /* 1023 */ 4843 /* 1024 */
4840 { NACLi_X87, 4844 { NACLi_X87,
4841 NACL_EMPTY_IFLAGS, 4845 NACL_EMPTY_IFLAGS,
4842 InstFcomp, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 4846 InstFcomp, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
4843 /* 1024 */ 4847 /* 1025 */
4844 { NACLi_X87, 4848 { NACLi_X87,
4845 NACL_EMPTY_IFLAGS, 4849 NACL_EMPTY_IFLAGS,
4846 InstFcomp, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 4850 InstFcomp, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
4847 /* 1025 */ 4851 /* 1026 */
4848 { NACLi_X87, 4852 { NACLi_X87,
4849 NACL_EMPTY_IFLAGS, 4853 NACL_EMPTY_IFLAGS,
4850 InstFcomp, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 4854 InstFcomp, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
4851 /* 1026 */ 4855 /* 1027 */
4852 { NACLi_X87, 4856 { NACLi_X87,
4853 NACL_EMPTY_IFLAGS, 4857 NACL_EMPTY_IFLAGS,
4854 InstFcomp, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 4858 InstFcomp, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
4855 /* 1027 */ 4859 /* 1028 */
4856 { NACLi_X87, 4860 { NACLi_X87,
4857 NACL_EMPTY_IFLAGS, 4861 NACL_EMPTY_IFLAGS,
4858 InstFcomp, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 4862 InstFcomp, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
4859 /* 1028 */ 4863 /* 1029 */
4860 { NACLi_X87, 4864 { NACLi_X87,
4861 NACL_EMPTY_IFLAGS, 4865 NACL_EMPTY_IFLAGS,
4862 InstFcomp, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 4866 InstFcomp, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
4863 /* 1029 */ 4867 /* 1030 */
4864 { NACLi_X87, 4868 { NACLi_X87,
4865 NACL_EMPTY_IFLAGS, 4869 NACL_EMPTY_IFLAGS,
4866 InstFsub, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4870 InstFsub, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4867 /* 1030 */ 4871 /* 1031 */
4868 { NACLi_X87, 4872 { NACLi_X87,
4869 NACL_EMPTY_IFLAGS, 4873 NACL_EMPTY_IFLAGS,
4870 InstFsub, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4874 InstFsub, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4871 /* 1031 */ 4875 /* 1032 */
4872 { NACLi_X87, 4876 { NACLi_X87,
4873 NACL_EMPTY_IFLAGS, 4877 NACL_EMPTY_IFLAGS,
4874 InstFsub, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4878 InstFsub, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4875 /* 1032 */ 4879 /* 1033 */
4876 { NACLi_X87, 4880 { NACLi_X87,
4877 NACL_EMPTY_IFLAGS, 4881 NACL_EMPTY_IFLAGS,
4878 InstFsub, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4882 InstFsub, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4879 /* 1033 */ 4883 /* 1034 */
4880 { NACLi_X87, 4884 { NACLi_X87,
4881 NACL_EMPTY_IFLAGS, 4885 NACL_EMPTY_IFLAGS,
4882 InstFsub, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4886 InstFsub, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4883 /* 1034 */ 4887 /* 1035 */
4884 { NACLi_X87, 4888 { NACLi_X87,
4885 NACL_EMPTY_IFLAGS, 4889 NACL_EMPTY_IFLAGS,
4886 InstFsub, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4890 InstFsub, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4887 /* 1035 */ 4891 /* 1036 */
4888 { NACLi_X87, 4892 { NACLi_X87,
4889 NACL_EMPTY_IFLAGS, 4893 NACL_EMPTY_IFLAGS,
4890 InstFsub, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4894 InstFsub, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4891 /* 1036 */ 4895 /* 1037 */
4892 { NACLi_X87, 4896 { NACLi_X87,
4893 NACL_EMPTY_IFLAGS, 4897 NACL_EMPTY_IFLAGS,
4894 InstFsub, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4898 InstFsub, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4895 /* 1037 */ 4899 /* 1038 */
4896 { NACLi_X87, 4900 { NACLi_X87,
4897 NACL_EMPTY_IFLAGS, 4901 NACL_EMPTY_IFLAGS,
4898 InstFsubr, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4902 InstFsubr, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4899 /* 1038 */ 4903 /* 1039 */
4900 { NACLi_X87, 4904 { NACLi_X87,
4901 NACL_EMPTY_IFLAGS, 4905 NACL_EMPTY_IFLAGS,
4902 InstFsubr, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4906 InstFsubr, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4903 /* 1039 */ 4907 /* 1040 */
4904 { NACLi_X87, 4908 { NACLi_X87,
4905 NACL_EMPTY_IFLAGS, 4909 NACL_EMPTY_IFLAGS,
4906 InstFsubr, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4910 InstFsubr, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4907 /* 1040 */ 4911 /* 1041 */
4908 { NACLi_X87, 4912 { NACLi_X87,
4909 NACL_EMPTY_IFLAGS, 4913 NACL_EMPTY_IFLAGS,
4910 InstFsubr, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4914 InstFsubr, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4911 /* 1041 */ 4915 /* 1042 */
4912 { NACLi_X87, 4916 { NACLi_X87,
4913 NACL_EMPTY_IFLAGS, 4917 NACL_EMPTY_IFLAGS,
4914 InstFsubr, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4918 InstFsubr, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4915 /* 1042 */ 4919 /* 1043 */
4916 { NACLi_X87, 4920 { NACLi_X87,
4917 NACL_EMPTY_IFLAGS, 4921 NACL_EMPTY_IFLAGS,
4918 InstFsubr, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4922 InstFsubr, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4919 /* 1043 */ 4923 /* 1044 */
4920 { NACLi_X87, 4924 { NACLi_X87,
4921 NACL_EMPTY_IFLAGS, 4925 NACL_EMPTY_IFLAGS,
4922 InstFsubr, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4926 InstFsubr, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4923 /* 1044 */ 4927 /* 1045 */
4924 { NACLi_X87, 4928 { NACLi_X87,
4925 NACL_EMPTY_IFLAGS, 4929 NACL_EMPTY_IFLAGS,
4926 InstFsubr, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4930 InstFsubr, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4927 /* 1045 */ 4931 /* 1046 */
4928 { NACLi_X87, 4932 { NACLi_X87,
4929 NACL_EMPTY_IFLAGS, 4933 NACL_EMPTY_IFLAGS,
4930 InstFdiv, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4934 InstFdiv, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4931 /* 1046 */ 4935 /* 1047 */
4932 { NACLi_X87, 4936 { NACLi_X87,
4933 NACL_EMPTY_IFLAGS, 4937 NACL_EMPTY_IFLAGS,
4934 InstFdiv, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4938 InstFdiv, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4935 /* 1047 */ 4939 /* 1048 */
4936 { NACLi_X87, 4940 { NACLi_X87,
4937 NACL_EMPTY_IFLAGS, 4941 NACL_EMPTY_IFLAGS,
4938 InstFdiv, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4942 InstFdiv, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4939 /* 1048 */ 4943 /* 1049 */
4940 { NACLi_X87, 4944 { NACLi_X87,
4941 NACL_EMPTY_IFLAGS, 4945 NACL_EMPTY_IFLAGS,
4942 InstFdiv, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4946 InstFdiv, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4943 /* 1049 */ 4947 /* 1050 */
4944 { NACLi_X87, 4948 { NACLi_X87,
4945 NACL_EMPTY_IFLAGS, 4949 NACL_EMPTY_IFLAGS,
4946 InstFdiv, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4950 InstFdiv, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4947 /* 1050 */ 4951 /* 1051 */
4948 { NACLi_X87, 4952 { NACLi_X87,
4949 NACL_EMPTY_IFLAGS, 4953 NACL_EMPTY_IFLAGS,
4950 InstFdiv, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4954 InstFdiv, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4951 /* 1051 */ 4955 /* 1052 */
4952 { NACLi_X87, 4956 { NACLi_X87,
4953 NACL_EMPTY_IFLAGS, 4957 NACL_EMPTY_IFLAGS,
4954 InstFdiv, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4958 InstFdiv, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4955 /* 1052 */ 4959 /* 1053 */
4956 { NACLi_X87, 4960 { NACLi_X87,
4957 NACL_EMPTY_IFLAGS, 4961 NACL_EMPTY_IFLAGS,
4958 InstFdiv, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4962 InstFdiv, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4959 /* 1053 */ 4963 /* 1054 */
4960 { NACLi_X87, 4964 { NACLi_X87,
4961 NACL_EMPTY_IFLAGS, 4965 NACL_EMPTY_IFLAGS,
4962 InstFdivr, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 4966 InstFdivr, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
4963 /* 1054 */ 4967 /* 1055 */
4964 { NACLi_X87, 4968 { NACLi_X87,
4965 NACL_EMPTY_IFLAGS, 4969 NACL_EMPTY_IFLAGS,
4966 InstFdivr, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 4970 InstFdivr, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
4967 /* 1055 */ 4971 /* 1056 */
4968 { NACLi_X87, 4972 { NACLi_X87,
4969 NACL_EMPTY_IFLAGS, 4973 NACL_EMPTY_IFLAGS,
4970 InstFdivr, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 4974 InstFdivr, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
4971 /* 1056 */ 4975 /* 1057 */
4972 { NACLi_X87, 4976 { NACLi_X87,
4973 NACL_EMPTY_IFLAGS, 4977 NACL_EMPTY_IFLAGS,
4974 InstFdivr, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 4978 InstFdivr, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
4975 /* 1057 */ 4979 /* 1058 */
4976 { NACLi_X87, 4980 { NACLi_X87,
4977 NACL_EMPTY_IFLAGS, 4981 NACL_EMPTY_IFLAGS,
4978 InstFdivr, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 4982 InstFdivr, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
4979 /* 1058 */ 4983 /* 1059 */
4980 { NACLi_X87, 4984 { NACLi_X87,
4981 NACL_EMPTY_IFLAGS, 4985 NACL_EMPTY_IFLAGS,
4982 InstFdivr, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 4986 InstFdivr, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
4983 /* 1059 */ 4987 /* 1060 */
4984 { NACLi_X87, 4988 { NACLi_X87,
4985 NACL_EMPTY_IFLAGS, 4989 NACL_EMPTY_IFLAGS,
4986 InstFdivr, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 4990 InstFdivr, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
4987 /* 1060 */ 4991 /* 1061 */
4988 { NACLi_X87, 4992 { NACLi_X87,
4989 NACL_EMPTY_IFLAGS, 4993 NACL_EMPTY_IFLAGS,
4990 InstFdivr, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 4994 InstFdivr, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
4991 /* 1061 */ 4995 /* 1062 */
4992 { NACLi_X87, 4996 { NACLi_X87,
4993 NACL_EMPTY_IFLAGS, 4997 NACL_EMPTY_IFLAGS,
4994 InstFld, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET }, 4998 InstFld, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET },
4995 /* 1062 */ 4999 /* 1063 */
4996 { NACLi_X87, 5000 { NACLi_X87,
4997 NACL_EMPTY_IFLAGS, 5001 NACL_EMPTY_IFLAGS,
4998 InstFld, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET }, 5002 InstFld, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET },
4999 /* 1063 */ 5003 /* 1064 */
5000 { NACLi_X87, 5004 { NACLi_X87,
5001 NACL_EMPTY_IFLAGS, 5005 NACL_EMPTY_IFLAGS,
5002 InstFld, 0x00, 2, 670, NACL_OPCODE_NULL_OFFSET }, 5006 InstFld, 0x00, 2, 670, NACL_OPCODE_NULL_OFFSET },
5003 /* 1064 */ 5007 /* 1065 */
5004 { NACLi_X87, 5008 { NACLi_X87,
5005 NACL_EMPTY_IFLAGS, 5009 NACL_EMPTY_IFLAGS,
5006 InstFld, 0x00, 2, 672, NACL_OPCODE_NULL_OFFSET }, 5010 InstFld, 0x00, 2, 672, NACL_OPCODE_NULL_OFFSET },
5007 /* 1065 */ 5011 /* 1066 */
5008 { NACLi_X87, 5012 { NACLi_X87,
5009 NACL_EMPTY_IFLAGS, 5013 NACL_EMPTY_IFLAGS,
5010 InstFld, 0x00, 2, 674, NACL_OPCODE_NULL_OFFSET }, 5014 InstFld, 0x00, 2, 674, NACL_OPCODE_NULL_OFFSET },
5011 /* 1066 */ 5015 /* 1067 */
5012 { NACLi_X87, 5016 { NACLi_X87,
5013 NACL_EMPTY_IFLAGS, 5017 NACL_EMPTY_IFLAGS,
5014 InstFld, 0x00, 2, 676, NACL_OPCODE_NULL_OFFSET }, 5018 InstFld, 0x00, 2, 676, NACL_OPCODE_NULL_OFFSET },
5015 /* 1067 */ 5019 /* 1068 */
5016 { NACLi_X87, 5020 { NACLi_X87,
5017 NACL_EMPTY_IFLAGS, 5021 NACL_EMPTY_IFLAGS,
5018 InstFld, 0x00, 2, 678, NACL_OPCODE_NULL_OFFSET }, 5022 InstFld, 0x00, 2, 678, NACL_OPCODE_NULL_OFFSET },
5019 /* 1068 */ 5023 /* 1069 */
5020 { NACLi_X87, 5024 { NACLi_X87,
5021 NACL_EMPTY_IFLAGS, 5025 NACL_EMPTY_IFLAGS,
5022 InstFld, 0x00, 2, 680, NACL_OPCODE_NULL_OFFSET }, 5026 InstFld, 0x00, 2, 680, NACL_OPCODE_NULL_OFFSET },
5023 /* 1069 */ 5027 /* 1070 */
5024 { NACLi_X87, 5028 { NACLi_X87,
5025 NACL_EMPTY_IFLAGS, 5029 NACL_EMPTY_IFLAGS,
5026 InstFxch, 0x00, 2, 682, NACL_OPCODE_NULL_OFFSET }, 5030 InstFxch, 0x00, 2, 682, NACL_OPCODE_NULL_OFFSET },
5027 /* 1070 */ 5031 /* 1071 */
5028 { NACLi_X87, 5032 { NACLi_X87,
5029 NACL_EMPTY_IFLAGS, 5033 NACL_EMPTY_IFLAGS,
5030 InstFxch, 0x00, 2, 684, NACL_OPCODE_NULL_OFFSET }, 5034 InstFxch, 0x00, 2, 684, NACL_OPCODE_NULL_OFFSET },
5031 /* 1071 */ 5035 /* 1072 */
5032 { NACLi_X87, 5036 { NACLi_X87,
5033 NACL_EMPTY_IFLAGS, 5037 NACL_EMPTY_IFLAGS,
5034 InstFxch, 0x00, 2, 686, NACL_OPCODE_NULL_OFFSET }, 5038 InstFxch, 0x00, 2, 686, NACL_OPCODE_NULL_OFFSET },
5035 /* 1072 */ 5039 /* 1073 */
5036 { NACLi_X87, 5040 { NACLi_X87,
5037 NACL_EMPTY_IFLAGS, 5041 NACL_EMPTY_IFLAGS,
5038 InstFxch, 0x00, 2, 688, NACL_OPCODE_NULL_OFFSET }, 5042 InstFxch, 0x00, 2, 688, NACL_OPCODE_NULL_OFFSET },
5039 /* 1073 */ 5043 /* 1074 */
5040 { NACLi_X87, 5044 { NACLi_X87,
5041 NACL_EMPTY_IFLAGS, 5045 NACL_EMPTY_IFLAGS,
5042 InstFxch, 0x00, 2, 690, NACL_OPCODE_NULL_OFFSET }, 5046 InstFxch, 0x00, 2, 690, NACL_OPCODE_NULL_OFFSET },
5043 /* 1074 */ 5047 /* 1075 */
5044 { NACLi_X87, 5048 { NACLi_X87,
5045 NACL_EMPTY_IFLAGS, 5049 NACL_EMPTY_IFLAGS,
5046 InstFxch, 0x00, 2, 692, NACL_OPCODE_NULL_OFFSET }, 5050 InstFxch, 0x00, 2, 692, NACL_OPCODE_NULL_OFFSET },
5047 /* 1075 */ 5051 /* 1076 */
5048 { NACLi_X87, 5052 { NACLi_X87,
5049 NACL_EMPTY_IFLAGS, 5053 NACL_EMPTY_IFLAGS,
5050 InstFxch, 0x00, 2, 694, NACL_OPCODE_NULL_OFFSET }, 5054 InstFxch, 0x00, 2, 694, NACL_OPCODE_NULL_OFFSET },
5051 /* 1076 */ 5055 /* 1077 */
5052 { NACLi_X87, 5056 { NACLi_X87,
5053 NACL_EMPTY_IFLAGS, 5057 NACL_EMPTY_IFLAGS,
5054 InstFxch, 0x00, 2, 696, NACL_OPCODE_NULL_OFFSET }, 5058 InstFxch, 0x00, 2, 696, NACL_OPCODE_NULL_OFFSET },
5055 /* 1077 */ 5059 /* 1078 */
5056 { NACLi_X87, 5060 { NACLi_X87,
5057 NACL_EMPTY_IFLAGS, 5061 NACL_EMPTY_IFLAGS,
5058 InstFnop, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 5062 InstFnop, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
5059 /* 1078 */ 5063 /* 1079 */
5060 { NACLi_X87, 5064 { NACLi_X87,
5061 NACL_EMPTY_IFLAGS, 5065 NACL_EMPTY_IFLAGS,
5062 InstFchs, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5066 InstFchs, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5063 /* 1079 */ 5067 /* 1080 */
5064 { NACLi_X87, 5068 { NACLi_X87,
5065 NACL_EMPTY_IFLAGS, 5069 NACL_EMPTY_IFLAGS,
5066 InstFabs, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5070 InstFabs, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5067 /* 1080 */ 5071 /* 1081 */
5068 { NACLi_X87, 5072 { NACLi_X87,
5069 NACL_EMPTY_IFLAGS, 5073 NACL_EMPTY_IFLAGS,
5070 InstFtst, 0x00, 1, 191, NACL_OPCODE_NULL_OFFSET }, 5074 InstFtst, 0x00, 1, 191, NACL_OPCODE_NULL_OFFSET },
5071 /* 1081 */ 5075 /* 1082 */
5072 { NACLi_X87, 5076 { NACLi_X87,
5073 NACL_EMPTY_IFLAGS, 5077 NACL_EMPTY_IFLAGS,
5074 InstFxam, 0x00, 1, 191, NACL_OPCODE_NULL_OFFSET }, 5078 InstFxam, 0x00, 1, 191, NACL_OPCODE_NULL_OFFSET },
5075 /* 1082 */ 5079 /* 1083 */
5076 { NACLi_X87, 5080 { NACLi_X87,
5077 NACL_EMPTY_IFLAGS, 5081 NACL_EMPTY_IFLAGS,
5078 InstFld1, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5082 InstFld1, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5079 /* 1083 */ 5083 /* 1084 */
5080 { NACLi_X87, 5084 { NACLi_X87,
5081 NACL_EMPTY_IFLAGS, 5085 NACL_EMPTY_IFLAGS,
5082 InstFldl2t, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5086 InstFldl2t, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5083 /* 1084 */ 5087 /* 1085 */
5084 { NACLi_X87, 5088 { NACLi_X87,
5085 NACL_EMPTY_IFLAGS, 5089 NACL_EMPTY_IFLAGS,
5086 InstFldl2e, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5090 InstFldl2e, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5087 /* 1085 */ 5091 /* 1086 */
5088 { NACLi_X87, 5092 { NACLi_X87,
5089 NACL_EMPTY_IFLAGS, 5093 NACL_EMPTY_IFLAGS,
5090 InstFldpi, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5094 InstFldpi, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5091 /* 1086 */ 5095 /* 1087 */
5092 { NACLi_X87, 5096 { NACLi_X87,
5093 NACL_EMPTY_IFLAGS, 5097 NACL_EMPTY_IFLAGS,
5094 InstFldlg2, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5098 InstFldlg2, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5095 /* 1087 */ 5099 /* 1088 */
5096 { NACLi_X87, 5100 { NACLi_X87,
5097 NACL_EMPTY_IFLAGS, 5101 NACL_EMPTY_IFLAGS,
5098 InstFldln2, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5102 InstFldln2, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5099 /* 1088 */ 5103 /* 1089 */
5100 { NACLi_X87, 5104 { NACLi_X87,
5101 NACL_EMPTY_IFLAGS, 5105 NACL_EMPTY_IFLAGS,
5102 InstFldz, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5106 InstFldz, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5103 /* 1089 */ 5107 /* 1090 */
5104 { NACLi_X87, 5108 { NACLi_X87,
5105 NACL_EMPTY_IFLAGS, 5109 NACL_EMPTY_IFLAGS,
5106 InstF2xm1, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5110 InstF2xm1, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5107 /* 1090 */ 5111 /* 1091 */
5108 { NACLi_X87, 5112 { NACLi_X87,
5109 NACL_EMPTY_IFLAGS, 5113 NACL_EMPTY_IFLAGS,
5110 InstFyl2x, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5114 InstFyl2x, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5111 /* 1091 */ 5115 /* 1092 */
5112 { NACLi_X87, 5116 { NACLi_X87,
5113 NACL_EMPTY_IFLAGS, 5117 NACL_EMPTY_IFLAGS,
5114 InstFptan, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET }, 5118 InstFptan, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET },
5115 /* 1092 */ 5119 /* 1093 */
5116 { NACLi_X87, 5120 { NACLi_X87,
5117 NACL_EMPTY_IFLAGS, 5121 NACL_EMPTY_IFLAGS,
5118 InstFpatan, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5122 InstFpatan, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5119 /* 1093 */ 5123 /* 1094 */
5120 { NACLi_X87, 5124 { NACLi_X87,
5121 NACL_EMPTY_IFLAGS, 5125 NACL_EMPTY_IFLAGS,
5122 InstFxtract, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET }, 5126 InstFxtract, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET },
5123 /* 1094 */ 5127 /* 1095 */
5124 { NACLi_X87, 5128 { NACLi_X87,
5125 NACL_EMPTY_IFLAGS, 5129 NACL_EMPTY_IFLAGS,
5126 InstFprem1, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5130 InstFprem1, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5127 /* 1095 */ 5131 /* 1096 */
5128 { NACLi_X87, 5132 { NACLi_X87,
5129 NACL_EMPTY_IFLAGS, 5133 NACL_EMPTY_IFLAGS,
5130 InstFdecstp, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 5134 InstFdecstp, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
5131 /* 1096 */ 5135 /* 1097 */
5132 { NACLi_X87, 5136 { NACLi_X87,
5133 NACL_EMPTY_IFLAGS, 5137 NACL_EMPTY_IFLAGS,
5134 InstFincstp, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 5138 InstFincstp, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
5135 /* 1097 */ 5139 /* 1098 */
5136 { NACLi_X87, 5140 { NACLi_X87,
5137 NACL_EMPTY_IFLAGS, 5141 NACL_EMPTY_IFLAGS,
5138 InstFprem, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5142 InstFprem, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5139 /* 1098 */ 5143 /* 1099 */
5140 { NACLi_X87, 5144 { NACLi_X87,
5141 NACL_EMPTY_IFLAGS, 5145 NACL_EMPTY_IFLAGS,
5142 InstFyl2xp1, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5146 InstFyl2xp1, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5143 /* 1099 */ 5147 /* 1100 */
5144 { NACLi_X87, 5148 { NACLi_X87,
5145 NACL_EMPTY_IFLAGS, 5149 NACL_EMPTY_IFLAGS,
5146 InstFsqrt, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5150 InstFsqrt, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5147 /* 1100 */ 5151 /* 1101 */
5148 { NACLi_X87_FSINCOS, 5152 { NACLi_X87_FSINCOS,
5149 NACL_EMPTY_IFLAGS, 5153 NACL_EMPTY_IFLAGS,
5150 InstFsincos, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET }, 5154 InstFsincos, 0x00, 2, 668, NACL_OPCODE_NULL_OFFSET },
5151 /* 1101 */ 5155 /* 1102 */
5152 { NACLi_X87, 5156 { NACLi_X87,
5153 NACL_EMPTY_IFLAGS, 5157 NACL_EMPTY_IFLAGS,
5154 InstFrndint, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5158 InstFrndint, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5155 /* 1102 */ 5159 /* 1103 */
5156 { NACLi_X87, 5160 { NACLi_X87,
5157 NACL_EMPTY_IFLAGS, 5161 NACL_EMPTY_IFLAGS,
5158 InstFscale, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5162 InstFscale, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5159 /* 1103 */ 5163 /* 1104 */
5160 { NACLi_X87, 5164 { NACLi_X87,
5161 NACL_EMPTY_IFLAGS, 5165 NACL_EMPTY_IFLAGS,
5162 InstFsin, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5166 InstFsin, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5163 /* 1104 */ 5167 /* 1105 */
5164 { NACLi_X87, 5168 { NACLi_X87,
5165 NACL_EMPTY_IFLAGS, 5169 NACL_EMPTY_IFLAGS,
5166 InstFcos, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET }, 5170 InstFcos, 0x00, 1, 189, NACL_OPCODE_NULL_OFFSET },
5167 /* 1105 */ 5171 /* 1106 */
5168 { NACLi_X87, 5172 { NACLi_X87,
5169 NACL_EMPTY_IFLAGS, 5173 NACL_EMPTY_IFLAGS,
5170 InstFcmovb, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5174 InstFcmovb, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5171 /* 1106 */ 5175 /* 1107 */
5172 { NACLi_X87, 5176 { NACLi_X87,
5173 NACL_EMPTY_IFLAGS, 5177 NACL_EMPTY_IFLAGS,
5174 InstFcmovb, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5178 InstFcmovb, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5175 /* 1107 */ 5179 /* 1108 */
5176 { NACLi_X87, 5180 { NACLi_X87,
5177 NACL_EMPTY_IFLAGS, 5181 NACL_EMPTY_IFLAGS,
5178 InstFcmovb, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5182 InstFcmovb, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5179 /* 1108 */ 5183 /* 1109 */
5180 { NACLi_X87, 5184 { NACLi_X87,
5181 NACL_EMPTY_IFLAGS, 5185 NACL_EMPTY_IFLAGS,
5182 InstFcmovb, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5186 InstFcmovb, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5183 /* 1109 */ 5187 /* 1110 */
5184 { NACLi_X87, 5188 { NACLi_X87,
5185 NACL_EMPTY_IFLAGS, 5189 NACL_EMPTY_IFLAGS,
5186 InstFcmovb, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5190 InstFcmovb, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5187 /* 1110 */ 5191 /* 1111 */
5188 { NACLi_X87, 5192 { NACLi_X87,
5189 NACL_EMPTY_IFLAGS, 5193 NACL_EMPTY_IFLAGS,
5190 InstFcmovb, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5194 InstFcmovb, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5191 /* 1111 */ 5195 /* 1112 */
5192 { NACLi_X87, 5196 { NACLi_X87,
5193 NACL_EMPTY_IFLAGS, 5197 NACL_EMPTY_IFLAGS,
5194 InstFcmovb, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5198 InstFcmovb, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5195 /* 1112 */ 5199 /* 1113 */
5196 { NACLi_X87, 5200 { NACLi_X87,
5197 NACL_EMPTY_IFLAGS, 5201 NACL_EMPTY_IFLAGS,
5198 InstFcmovb, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5202 InstFcmovb, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5199 /* 1113 */ 5203 /* 1114 */
5200 { NACLi_X87, 5204 { NACLi_X87,
5201 NACL_EMPTY_IFLAGS, 5205 NACL_EMPTY_IFLAGS,
5202 InstFcmove, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5206 InstFcmove, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5203 /* 1114 */ 5207 /* 1115 */
5204 { NACLi_X87, 5208 { NACLi_X87,
5205 NACL_EMPTY_IFLAGS, 5209 NACL_EMPTY_IFLAGS,
5206 InstFcmove, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5210 InstFcmove, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5207 /* 1115 */ 5211 /* 1116 */
5208 { NACLi_X87, 5212 { NACLi_X87,
5209 NACL_EMPTY_IFLAGS, 5213 NACL_EMPTY_IFLAGS,
5210 InstFcmove, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5214 InstFcmove, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5211 /* 1116 */ 5215 /* 1117 */
5212 { NACLi_X87, 5216 { NACLi_X87,
5213 NACL_EMPTY_IFLAGS, 5217 NACL_EMPTY_IFLAGS,
5214 InstFcmove, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5218 InstFcmove, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5215 /* 1117 */ 5219 /* 1118 */
5216 { NACLi_X87, 5220 { NACLi_X87,
5217 NACL_EMPTY_IFLAGS, 5221 NACL_EMPTY_IFLAGS,
5218 InstFcmove, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5222 InstFcmove, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5219 /* 1118 */ 5223 /* 1119 */
5220 { NACLi_X87, 5224 { NACLi_X87,
5221 NACL_EMPTY_IFLAGS, 5225 NACL_EMPTY_IFLAGS,
5222 InstFcmove, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5226 InstFcmove, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5223 /* 1119 */ 5227 /* 1120 */
5224 { NACLi_X87, 5228 { NACLi_X87,
5225 NACL_EMPTY_IFLAGS, 5229 NACL_EMPTY_IFLAGS,
5226 InstFcmove, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5230 InstFcmove, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5227 /* 1120 */ 5231 /* 1121 */
5228 { NACLi_X87, 5232 { NACLi_X87,
5229 NACL_EMPTY_IFLAGS, 5233 NACL_EMPTY_IFLAGS,
5230 InstFcmove, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5234 InstFcmove, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5231 /* 1121 */ 5235 /* 1122 */
5232 { NACLi_X87, 5236 { NACLi_X87,
5233 NACL_EMPTY_IFLAGS, 5237 NACL_EMPTY_IFLAGS,
5234 InstFcmovbe, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5238 InstFcmovbe, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5235 /* 1122 */ 5239 /* 1123 */
5236 { NACLi_X87, 5240 { NACLi_X87,
5237 NACL_EMPTY_IFLAGS, 5241 NACL_EMPTY_IFLAGS,
5238 InstFcmovbe, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5242 InstFcmovbe, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5239 /* 1123 */ 5243 /* 1124 */
5240 { NACLi_X87, 5244 { NACLi_X87,
5241 NACL_EMPTY_IFLAGS, 5245 NACL_EMPTY_IFLAGS,
5242 InstFcmovbe, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5246 InstFcmovbe, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5243 /* 1124 */ 5247 /* 1125 */
5244 { NACLi_X87, 5248 { NACLi_X87,
5245 NACL_EMPTY_IFLAGS, 5249 NACL_EMPTY_IFLAGS,
5246 InstFcmovbe, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5250 InstFcmovbe, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5247 /* 1125 */ 5251 /* 1126 */
5248 { NACLi_X87, 5252 { NACLi_X87,
5249 NACL_EMPTY_IFLAGS, 5253 NACL_EMPTY_IFLAGS,
5250 InstFcmovbe, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5254 InstFcmovbe, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5251 /* 1126 */ 5255 /* 1127 */
5252 { NACLi_X87, 5256 { NACLi_X87,
5253 NACL_EMPTY_IFLAGS, 5257 NACL_EMPTY_IFLAGS,
5254 InstFcmovbe, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5258 InstFcmovbe, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5255 /* 1127 */ 5259 /* 1128 */
5256 { NACLi_X87, 5260 { NACLi_X87,
5257 NACL_EMPTY_IFLAGS, 5261 NACL_EMPTY_IFLAGS,
5258 InstFcmovbe, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5262 InstFcmovbe, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5259 /* 1128 */ 5263 /* 1129 */
5260 { NACLi_X87, 5264 { NACLi_X87,
5261 NACL_EMPTY_IFLAGS, 5265 NACL_EMPTY_IFLAGS,
5262 InstFcmovbe, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5266 InstFcmovbe, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5263 /* 1129 */ 5267 /* 1130 */
5264 { NACLi_X87, 5268 { NACLi_X87,
5265 NACL_EMPTY_IFLAGS, 5269 NACL_EMPTY_IFLAGS,
5266 InstFcmovu, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5270 InstFcmovu, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5267 /* 1130 */ 5271 /* 1131 */
5268 { NACLi_X87, 5272 { NACLi_X87,
5269 NACL_EMPTY_IFLAGS, 5273 NACL_EMPTY_IFLAGS,
5270 InstFcmovu, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5274 InstFcmovu, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5271 /* 1131 */ 5275 /* 1132 */
5272 { NACLi_X87, 5276 { NACLi_X87,
5273 NACL_EMPTY_IFLAGS, 5277 NACL_EMPTY_IFLAGS,
5274 InstFcmovu, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5278 InstFcmovu, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5275 /* 1132 */ 5279 /* 1133 */
5276 { NACLi_X87, 5280 { NACLi_X87,
5277 NACL_EMPTY_IFLAGS, 5281 NACL_EMPTY_IFLAGS,
5278 InstFcmovu, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5282 InstFcmovu, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5279 /* 1133 */ 5283 /* 1134 */
5280 { NACLi_X87, 5284 { NACLi_X87,
5281 NACL_EMPTY_IFLAGS, 5285 NACL_EMPTY_IFLAGS,
5282 InstFcmovu, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5286 InstFcmovu, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5283 /* 1134 */ 5287 /* 1135 */
5284 { NACLi_X87, 5288 { NACLi_X87,
5285 NACL_EMPTY_IFLAGS, 5289 NACL_EMPTY_IFLAGS,
5286 InstFcmovu, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5290 InstFcmovu, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5287 /* 1135 */ 5291 /* 1136 */
5288 { NACLi_X87, 5292 { NACLi_X87,
5289 NACL_EMPTY_IFLAGS, 5293 NACL_EMPTY_IFLAGS,
5290 InstFcmovu, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5294 InstFcmovu, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5291 /* 1136 */ 5295 /* 1137 */
5292 { NACLi_X87, 5296 { NACLi_X87,
5293 NACL_EMPTY_IFLAGS, 5297 NACL_EMPTY_IFLAGS,
5294 InstFcmovu, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5298 InstFcmovu, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5295 /* 1137 */ 5299 /* 1138 */
5296 { NACLi_X87, 5300 { NACLi_X87,
5297 NACL_EMPTY_IFLAGS, 5301 NACL_EMPTY_IFLAGS,
5298 InstFucompp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5302 InstFucompp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5299 /* 1138 */ 5303 /* 1139 */
5300 { NACLi_X87, 5304 { NACLi_X87,
5301 NACL_EMPTY_IFLAGS, 5305 NACL_EMPTY_IFLAGS,
5302 InstFcmovnb, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5306 InstFcmovnb, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5303 /* 1139 */ 5307 /* 1140 */
5304 { NACLi_X87, 5308 { NACLi_X87,
5305 NACL_EMPTY_IFLAGS, 5309 NACL_EMPTY_IFLAGS,
5306 InstFcmovnb, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5310 InstFcmovnb, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5307 /* 1140 */ 5311 /* 1141 */
5308 { NACLi_X87, 5312 { NACLi_X87,
5309 NACL_EMPTY_IFLAGS, 5313 NACL_EMPTY_IFLAGS,
5310 InstFcmovnb, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5314 InstFcmovnb, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5311 /* 1141 */ 5315 /* 1142 */
5312 { NACLi_X87, 5316 { NACLi_X87,
5313 NACL_EMPTY_IFLAGS, 5317 NACL_EMPTY_IFLAGS,
5314 InstFcmovnb, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5318 InstFcmovnb, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5315 /* 1142 */ 5319 /* 1143 */
5316 { NACLi_X87, 5320 { NACLi_X87,
5317 NACL_EMPTY_IFLAGS, 5321 NACL_EMPTY_IFLAGS,
5318 InstFcmovnb, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5322 InstFcmovnb, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5319 /* 1143 */ 5323 /* 1144 */
5320 { NACLi_X87, 5324 { NACLi_X87,
5321 NACL_EMPTY_IFLAGS, 5325 NACL_EMPTY_IFLAGS,
5322 InstFcmovnb, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5326 InstFcmovnb, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5323 /* 1144 */ 5327 /* 1145 */
5324 { NACLi_X87, 5328 { NACLi_X87,
5325 NACL_EMPTY_IFLAGS, 5329 NACL_EMPTY_IFLAGS,
5326 InstFcmovnb, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5330 InstFcmovnb, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5327 /* 1145 */ 5331 /* 1146 */
5328 { NACLi_X87, 5332 { NACLi_X87,
5329 NACL_EMPTY_IFLAGS, 5333 NACL_EMPTY_IFLAGS,
5330 InstFcmovnb, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5334 InstFcmovnb, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5331 /* 1146 */ 5335 /* 1147 */
5332 { NACLi_X87, 5336 { NACLi_X87,
5333 NACL_EMPTY_IFLAGS, 5337 NACL_EMPTY_IFLAGS,
5334 InstFcmovne, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5338 InstFcmovne, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5335 /* 1147 */ 5339 /* 1148 */
5336 { NACLi_X87, 5340 { NACLi_X87,
5337 NACL_EMPTY_IFLAGS, 5341 NACL_EMPTY_IFLAGS,
5338 InstFcmovne, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5342 InstFcmovne, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5339 /* 1148 */ 5343 /* 1149 */
5340 { NACLi_X87, 5344 { NACLi_X87,
5341 NACL_EMPTY_IFLAGS, 5345 NACL_EMPTY_IFLAGS,
5342 InstFcmovne, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5346 InstFcmovne, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5343 /* 1149 */ 5347 /* 1150 */
5344 { NACLi_X87, 5348 { NACLi_X87,
5345 NACL_EMPTY_IFLAGS, 5349 NACL_EMPTY_IFLAGS,
5346 InstFcmovne, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5350 InstFcmovne, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5347 /* 1150 */ 5351 /* 1151 */
5348 { NACLi_X87, 5352 { NACLi_X87,
5349 NACL_EMPTY_IFLAGS, 5353 NACL_EMPTY_IFLAGS,
5350 InstFcmovne, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5354 InstFcmovne, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5351 /* 1151 */ 5355 /* 1152 */
5352 { NACLi_X87, 5356 { NACLi_X87,
5353 NACL_EMPTY_IFLAGS, 5357 NACL_EMPTY_IFLAGS,
5354 InstFcmovne, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5358 InstFcmovne, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5355 /* 1152 */ 5359 /* 1153 */
5356 { NACLi_X87, 5360 { NACLi_X87,
5357 NACL_EMPTY_IFLAGS, 5361 NACL_EMPTY_IFLAGS,
5358 InstFcmovne, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5362 InstFcmovne, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5359 /* 1153 */ 5363 /* 1154 */
5360 { NACLi_X87, 5364 { NACLi_X87,
5361 NACL_EMPTY_IFLAGS, 5365 NACL_EMPTY_IFLAGS,
5362 InstFcmovne, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5366 InstFcmovne, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5363 /* 1154 */ 5367 /* 1155 */
5364 { NACLi_X87, 5368 { NACLi_X87,
5365 NACL_EMPTY_IFLAGS, 5369 NACL_EMPTY_IFLAGS,
5366 InstFcmovnbe, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5370 InstFcmovnbe, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5367 /* 1155 */ 5371 /* 1156 */
5368 { NACLi_X87, 5372 { NACLi_X87,
5369 NACL_EMPTY_IFLAGS, 5373 NACL_EMPTY_IFLAGS,
5370 InstFcmovnbe, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5374 InstFcmovnbe, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5371 /* 1156 */ 5375 /* 1157 */
5372 { NACLi_X87, 5376 { NACLi_X87,
5373 NACL_EMPTY_IFLAGS, 5377 NACL_EMPTY_IFLAGS,
5374 InstFcmovnbe, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5378 InstFcmovnbe, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5375 /* 1157 */ 5379 /* 1158 */
5376 { NACLi_X87, 5380 { NACLi_X87,
5377 NACL_EMPTY_IFLAGS, 5381 NACL_EMPTY_IFLAGS,
5378 InstFcmovnbe, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5382 InstFcmovnbe, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5379 /* 1158 */ 5383 /* 1159 */
5380 { NACLi_X87, 5384 { NACLi_X87,
5381 NACL_EMPTY_IFLAGS, 5385 NACL_EMPTY_IFLAGS,
5382 InstFcmovnbe, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5386 InstFcmovnbe, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5383 /* 1159 */ 5387 /* 1160 */
5384 { NACLi_X87, 5388 { NACLi_X87,
5385 NACL_EMPTY_IFLAGS, 5389 NACL_EMPTY_IFLAGS,
5386 InstFcmovnbe, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5390 InstFcmovnbe, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5387 /* 1160 */ 5391 /* 1161 */
5388 { NACLi_X87, 5392 { NACLi_X87,
5389 NACL_EMPTY_IFLAGS, 5393 NACL_EMPTY_IFLAGS,
5390 InstFcmovnbe, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5394 InstFcmovnbe, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5391 /* 1161 */ 5395 /* 1162 */
5392 { NACLi_X87, 5396 { NACLi_X87,
5393 NACL_EMPTY_IFLAGS, 5397 NACL_EMPTY_IFLAGS,
5394 InstFcmovnbe, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5398 InstFcmovnbe, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5395 /* 1162 */ 5399 /* 1163 */
5396 { NACLi_X87, 5400 { NACLi_X87,
5397 NACL_EMPTY_IFLAGS, 5401 NACL_EMPTY_IFLAGS,
5398 InstFcmovnu, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5402 InstFcmovnu, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5399 /* 1163 */ 5403 /* 1164 */
5400 { NACLi_X87, 5404 { NACLi_X87,
5401 NACL_EMPTY_IFLAGS, 5405 NACL_EMPTY_IFLAGS,
5402 InstFcmovnu, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET }, 5406 InstFcmovnu, 0x00, 2, 636, NACL_OPCODE_NULL_OFFSET },
5403 /* 1164 */ 5407 /* 1165 */
5404 { NACLi_X87, 5408 { NACLi_X87,
5405 NACL_EMPTY_IFLAGS, 5409 NACL_EMPTY_IFLAGS,
5406 InstFcmovnu, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET }, 5410 InstFcmovnu, 0x00, 2, 638, NACL_OPCODE_NULL_OFFSET },
5407 /* 1165 */ 5411 /* 1166 */
5408 { NACLi_X87, 5412 { NACLi_X87,
5409 NACL_EMPTY_IFLAGS, 5413 NACL_EMPTY_IFLAGS,
5410 InstFcmovnu, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET }, 5414 InstFcmovnu, 0x00, 2, 640, NACL_OPCODE_NULL_OFFSET },
5411 /* 1166 */ 5415 /* 1167 */
5412 { NACLi_X87, 5416 { NACLi_X87,
5413 NACL_EMPTY_IFLAGS, 5417 NACL_EMPTY_IFLAGS,
5414 InstFcmovnu, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET }, 5418 InstFcmovnu, 0x00, 2, 642, NACL_OPCODE_NULL_OFFSET },
5415 /* 1167 */ 5419 /* 1168 */
5416 { NACLi_X87, 5420 { NACLi_X87,
5417 NACL_EMPTY_IFLAGS, 5421 NACL_EMPTY_IFLAGS,
5418 InstFcmovnu, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET }, 5422 InstFcmovnu, 0x00, 2, 644, NACL_OPCODE_NULL_OFFSET },
5419 /* 1168 */ 5423 /* 1169 */
5420 { NACLi_X87, 5424 { NACLi_X87,
5421 NACL_EMPTY_IFLAGS, 5425 NACL_EMPTY_IFLAGS,
5422 InstFcmovnu, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET }, 5426 InstFcmovnu, 0x00, 2, 646, NACL_OPCODE_NULL_OFFSET },
5423 /* 1169 */ 5427 /* 1170 */
5424 { NACLi_X87, 5428 { NACLi_X87,
5425 NACL_EMPTY_IFLAGS, 5429 NACL_EMPTY_IFLAGS,
5426 InstFcmovnu, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET }, 5430 InstFcmovnu, 0x00, 2, 648, NACL_OPCODE_NULL_OFFSET },
5427 /* 1170 */ 5431 /* 1171 */
5428 { NACLi_X87, 5432 { NACLi_X87,
5429 NACL_EMPTY_IFLAGS, 5433 NACL_EMPTY_IFLAGS,
5430 InstFnclex, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 5434 InstFnclex, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
5431 /* 1171 */ 5435 /* 1172 */
5432 { NACLi_X87, 5436 { NACLi_X87,
5433 NACL_EMPTY_IFLAGS, 5437 NACL_EMPTY_IFLAGS,
5434 InstFninit, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 5438 InstFninit, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
5435 /* 1172 */ 5439 /* 1173 */
5436 { NACLi_X87, 5440 { NACLi_X87,
5437 NACL_EMPTY_IFLAGS, 5441 NACL_EMPTY_IFLAGS,
5438 InstFucomi, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 5442 InstFucomi, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
5439 /* 1173 */ 5443 /* 1174 */
5440 { NACLi_X87, 5444 { NACLi_X87,
5441 NACL_EMPTY_IFLAGS, 5445 NACL_EMPTY_IFLAGS,
5442 InstFucomi, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5446 InstFucomi, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5443 /* 1174 */ 5447 /* 1175 */
5444 { NACLi_X87, 5448 { NACLi_X87,
5445 NACL_EMPTY_IFLAGS, 5449 NACL_EMPTY_IFLAGS,
5446 InstFucomi, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 5450 InstFucomi, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
5447 /* 1175 */ 5451 /* 1176 */
5448 { NACLi_X87, 5452 { NACLi_X87,
5449 NACL_EMPTY_IFLAGS, 5453 NACL_EMPTY_IFLAGS,
5450 InstFucomi, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 5454 InstFucomi, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
5451 /* 1176 */ 5455 /* 1177 */
5452 { NACLi_X87, 5456 { NACLi_X87,
5453 NACL_EMPTY_IFLAGS, 5457 NACL_EMPTY_IFLAGS,
5454 InstFucomi, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 5458 InstFucomi, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
5455 /* 1177 */ 5459 /* 1178 */
5456 { NACLi_X87, 5460 { NACLi_X87,
5457 NACL_EMPTY_IFLAGS, 5461 NACL_EMPTY_IFLAGS,
5458 InstFucomi, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 5462 InstFucomi, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
5459 /* 1178 */ 5463 /* 1179 */
5460 { NACLi_X87, 5464 { NACLi_X87,
5461 NACL_EMPTY_IFLAGS, 5465 NACL_EMPTY_IFLAGS,
5462 InstFucomi, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 5466 InstFucomi, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
5463 /* 1179 */ 5467 /* 1180 */
5464 { NACLi_X87, 5468 { NACLi_X87,
5465 NACL_EMPTY_IFLAGS, 5469 NACL_EMPTY_IFLAGS,
5466 InstFucomi, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 5470 InstFucomi, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
5467 /* 1180 */ 5471 /* 1181 */
5468 { NACLi_X87, 5472 { NACLi_X87,
5469 NACL_EMPTY_IFLAGS, 5473 NACL_EMPTY_IFLAGS,
5470 InstFcomi, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 5474 InstFcomi, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
5471 /* 1181 */ 5475 /* 1182 */
5472 { NACLi_X87, 5476 { NACLi_X87,
5473 NACL_EMPTY_IFLAGS, 5477 NACL_EMPTY_IFLAGS,
5474 InstFcomi, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5478 InstFcomi, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5475 /* 1182 */ 5479 /* 1183 */
5476 { NACLi_X87, 5480 { NACLi_X87,
5477 NACL_EMPTY_IFLAGS, 5481 NACL_EMPTY_IFLAGS,
5478 InstFcomi, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 5482 InstFcomi, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
5479 /* 1183 */ 5483 /* 1184 */
5480 { NACLi_X87, 5484 { NACLi_X87,
5481 NACL_EMPTY_IFLAGS, 5485 NACL_EMPTY_IFLAGS,
5482 InstFcomi, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 5486 InstFcomi, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
5483 /* 1184 */ 5487 /* 1185 */
5484 { NACLi_X87, 5488 { NACLi_X87,
5485 NACL_EMPTY_IFLAGS, 5489 NACL_EMPTY_IFLAGS,
5486 InstFcomi, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 5490 InstFcomi, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
5487 /* 1185 */ 5491 /* 1186 */
5488 { NACLi_X87, 5492 { NACLi_X87,
5489 NACL_EMPTY_IFLAGS, 5493 NACL_EMPTY_IFLAGS,
5490 InstFcomi, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 5494 InstFcomi, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
5491 /* 1186 */ 5495 /* 1187 */
5492 { NACLi_X87, 5496 { NACLi_X87,
5493 NACL_EMPTY_IFLAGS, 5497 NACL_EMPTY_IFLAGS,
5494 InstFcomi, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 5498 InstFcomi, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
5495 /* 1187 */ 5499 /* 1188 */
5496 { NACLi_X87, 5500 { NACLi_X87,
5497 NACL_EMPTY_IFLAGS, 5501 NACL_EMPTY_IFLAGS,
5498 InstFcomi, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 5502 InstFcomi, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
5499 /* 1188 */ 5503 /* 1189 */
5500 { NACLi_X87, 5504 { NACLi_X87,
5501 NACL_EMPTY_IFLAGS, 5505 NACL_EMPTY_IFLAGS,
5502 InstFadd, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5506 InstFadd, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5503 /* 1189 */ 5507 /* 1190 */
5504 { NACLi_X87, 5508 { NACLi_X87,
5505 NACL_EMPTY_IFLAGS, 5509 NACL_EMPTY_IFLAGS,
5506 InstFadd, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5510 InstFadd, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5507 /* 1190 */ 5511 /* 1191 */
5508 { NACLi_X87, 5512 { NACLi_X87,
5509 NACL_EMPTY_IFLAGS, 5513 NACL_EMPTY_IFLAGS,
5510 InstFadd, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5514 InstFadd, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5511 /* 1191 */ 5515 /* 1192 */
5512 { NACLi_X87, 5516 { NACLi_X87,
5513 NACL_EMPTY_IFLAGS, 5517 NACL_EMPTY_IFLAGS,
5514 InstFadd, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5518 InstFadd, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5515 /* 1192 */ 5519 /* 1193 */
5516 { NACLi_X87, 5520 { NACLi_X87,
5517 NACL_EMPTY_IFLAGS, 5521 NACL_EMPTY_IFLAGS,
5518 InstFadd, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5522 InstFadd, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5519 /* 1193 */ 5523 /* 1194 */
5520 { NACLi_X87, 5524 { NACLi_X87,
5521 NACL_EMPTY_IFLAGS, 5525 NACL_EMPTY_IFLAGS,
5522 InstFadd, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5526 InstFadd, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5523 /* 1194 */ 5527 /* 1195 */
5524 { NACLi_X87, 5528 { NACLi_X87,
5525 NACL_EMPTY_IFLAGS, 5529 NACL_EMPTY_IFLAGS,
5526 InstFadd, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5530 InstFadd, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5527 /* 1195 */ 5531 /* 1196 */
5528 { NACLi_X87, 5532 { NACLi_X87,
5529 NACL_EMPTY_IFLAGS, 5533 NACL_EMPTY_IFLAGS,
5530 InstFmul, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5534 InstFmul, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5531 /* 1196 */ 5535 /* 1197 */
5532 { NACLi_X87, 5536 { NACLi_X87,
5533 NACL_EMPTY_IFLAGS, 5537 NACL_EMPTY_IFLAGS,
5534 InstFmul, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5538 InstFmul, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5535 /* 1197 */ 5539 /* 1198 */
5536 { NACLi_X87, 5540 { NACLi_X87,
5537 NACL_EMPTY_IFLAGS, 5541 NACL_EMPTY_IFLAGS,
5538 InstFmul, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5542 InstFmul, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5539 /* 1198 */ 5543 /* 1199 */
5540 { NACLi_X87, 5544 { NACLi_X87,
5541 NACL_EMPTY_IFLAGS, 5545 NACL_EMPTY_IFLAGS,
5542 InstFmul, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5546 InstFmul, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5543 /* 1199 */ 5547 /* 1200 */
5544 { NACLi_X87, 5548 { NACLi_X87,
5545 NACL_EMPTY_IFLAGS, 5549 NACL_EMPTY_IFLAGS,
5546 InstFmul, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5550 InstFmul, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5547 /* 1200 */ 5551 /* 1201 */
5548 { NACLi_X87, 5552 { NACLi_X87,
5549 NACL_EMPTY_IFLAGS, 5553 NACL_EMPTY_IFLAGS,
5550 InstFmul, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5554 InstFmul, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5551 /* 1201 */ 5555 /* 1202 */
5552 { NACLi_X87, 5556 { NACLi_X87,
5553 NACL_EMPTY_IFLAGS, 5557 NACL_EMPTY_IFLAGS,
5554 InstFmul, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5558 InstFmul, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5555 /* 1202 */ 5559 /* 1203 */
5556 { NACLi_X87, 5560 { NACLi_X87,
5557 NACL_EMPTY_IFLAGS, 5561 NACL_EMPTY_IFLAGS,
5558 InstFsubr, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5562 InstFsubr, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5559 /* 1203 */ 5563 /* 1204 */
5560 { NACLi_X87, 5564 { NACLi_X87,
5561 NACL_EMPTY_IFLAGS, 5565 NACL_EMPTY_IFLAGS,
5562 InstFsubr, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5566 InstFsubr, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5563 /* 1204 */ 5567 /* 1205 */
5564 { NACLi_X87, 5568 { NACLi_X87,
5565 NACL_EMPTY_IFLAGS, 5569 NACL_EMPTY_IFLAGS,
5566 InstFsubr, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5570 InstFsubr, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5567 /* 1205 */ 5571 /* 1206 */
5568 { NACLi_X87, 5572 { NACLi_X87,
5569 NACL_EMPTY_IFLAGS, 5573 NACL_EMPTY_IFLAGS,
5570 InstFsubr, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5574 InstFsubr, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5571 /* 1206 */ 5575 /* 1207 */
5572 { NACLi_X87, 5576 { NACLi_X87,
5573 NACL_EMPTY_IFLAGS, 5577 NACL_EMPTY_IFLAGS,
5574 InstFsubr, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5578 InstFsubr, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5575 /* 1207 */ 5579 /* 1208 */
5576 { NACLi_X87, 5580 { NACLi_X87,
5577 NACL_EMPTY_IFLAGS, 5581 NACL_EMPTY_IFLAGS,
5578 InstFsubr, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5582 InstFsubr, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5579 /* 1208 */ 5583 /* 1209 */
5580 { NACLi_X87, 5584 { NACLi_X87,
5581 NACL_EMPTY_IFLAGS, 5585 NACL_EMPTY_IFLAGS,
5582 InstFsubr, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5586 InstFsubr, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5583 /* 1209 */ 5587 /* 1210 */
5584 { NACLi_X87, 5588 { NACLi_X87,
5585 NACL_EMPTY_IFLAGS, 5589 NACL_EMPTY_IFLAGS,
5586 InstFsub, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5590 InstFsub, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5587 /* 1210 */ 5591 /* 1211 */
5588 { NACLi_X87, 5592 { NACLi_X87,
5589 NACL_EMPTY_IFLAGS, 5593 NACL_EMPTY_IFLAGS,
5590 InstFsub, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5594 InstFsub, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5591 /* 1211 */ 5595 /* 1212 */
5592 { NACLi_X87, 5596 { NACLi_X87,
5593 NACL_EMPTY_IFLAGS, 5597 NACL_EMPTY_IFLAGS,
5594 InstFsub, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5598 InstFsub, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5595 /* 1212 */ 5599 /* 1213 */
5596 { NACLi_X87, 5600 { NACLi_X87,
5597 NACL_EMPTY_IFLAGS, 5601 NACL_EMPTY_IFLAGS,
5598 InstFsub, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5602 InstFsub, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5599 /* 1213 */ 5603 /* 1214 */
5600 { NACLi_X87, 5604 { NACLi_X87,
5601 NACL_EMPTY_IFLAGS, 5605 NACL_EMPTY_IFLAGS,
5602 InstFsub, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5606 InstFsub, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5603 /* 1214 */ 5607 /* 1215 */
5604 { NACLi_X87, 5608 { NACLi_X87,
5605 NACL_EMPTY_IFLAGS, 5609 NACL_EMPTY_IFLAGS,
5606 InstFsub, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5610 InstFsub, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5607 /* 1215 */ 5611 /* 1216 */
5608 { NACLi_X87, 5612 { NACLi_X87,
5609 NACL_EMPTY_IFLAGS, 5613 NACL_EMPTY_IFLAGS,
5610 InstFsub, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5614 InstFsub, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5611 /* 1216 */ 5615 /* 1217 */
5612 { NACLi_X87, 5616 { NACLi_X87,
5613 NACL_EMPTY_IFLAGS, 5617 NACL_EMPTY_IFLAGS,
5614 InstFdivr, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5618 InstFdivr, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5615 /* 1217 */ 5619 /* 1218 */
5616 { NACLi_X87, 5620 { NACLi_X87,
5617 NACL_EMPTY_IFLAGS, 5621 NACL_EMPTY_IFLAGS,
5618 InstFdivr, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5622 InstFdivr, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5619 /* 1218 */ 5623 /* 1219 */
5620 { NACLi_X87, 5624 { NACLi_X87,
5621 NACL_EMPTY_IFLAGS, 5625 NACL_EMPTY_IFLAGS,
5622 InstFdivr, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5626 InstFdivr, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5623 /* 1219 */ 5627 /* 1220 */
5624 { NACLi_X87, 5628 { NACLi_X87,
5625 NACL_EMPTY_IFLAGS, 5629 NACL_EMPTY_IFLAGS,
5626 InstFdivr, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5630 InstFdivr, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5627 /* 1220 */ 5631 /* 1221 */
5628 { NACLi_X87, 5632 { NACLi_X87,
5629 NACL_EMPTY_IFLAGS, 5633 NACL_EMPTY_IFLAGS,
5630 InstFdivr, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5634 InstFdivr, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5631 /* 1221 */ 5635 /* 1222 */
5632 { NACLi_X87, 5636 { NACLi_X87,
5633 NACL_EMPTY_IFLAGS, 5637 NACL_EMPTY_IFLAGS,
5634 InstFdivr, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5638 InstFdivr, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5635 /* 1222 */ 5639 /* 1223 */
5636 { NACLi_X87, 5640 { NACLi_X87,
5637 NACL_EMPTY_IFLAGS, 5641 NACL_EMPTY_IFLAGS,
5638 InstFdivr, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5642 InstFdivr, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5639 /* 1223 */ 5643 /* 1224 */
5640 { NACLi_X87, 5644 { NACLi_X87,
5641 NACL_EMPTY_IFLAGS, 5645 NACL_EMPTY_IFLAGS,
5642 InstFdiv, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5646 InstFdiv, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5643 /* 1224 */ 5647 /* 1225 */
5644 { NACLi_X87, 5648 { NACLi_X87,
5645 NACL_EMPTY_IFLAGS, 5649 NACL_EMPTY_IFLAGS,
5646 InstFdiv, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5650 InstFdiv, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5647 /* 1225 */ 5651 /* 1226 */
5648 { NACLi_X87, 5652 { NACLi_X87,
5649 NACL_EMPTY_IFLAGS, 5653 NACL_EMPTY_IFLAGS,
5650 InstFdiv, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5654 InstFdiv, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5651 /* 1226 */ 5655 /* 1227 */
5652 { NACLi_X87, 5656 { NACLi_X87,
5653 NACL_EMPTY_IFLAGS, 5657 NACL_EMPTY_IFLAGS,
5654 InstFdiv, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5658 InstFdiv, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5655 /* 1227 */ 5659 /* 1228 */
5656 { NACLi_X87, 5660 { NACLi_X87,
5657 NACL_EMPTY_IFLAGS, 5661 NACL_EMPTY_IFLAGS,
5658 InstFdiv, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5662 InstFdiv, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5659 /* 1228 */ 5663 /* 1229 */
5660 { NACLi_X87, 5664 { NACLi_X87,
5661 NACL_EMPTY_IFLAGS, 5665 NACL_EMPTY_IFLAGS,
5662 InstFdiv, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5666 InstFdiv, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5663 /* 1229 */ 5667 /* 1230 */
5664 { NACLi_X87, 5668 { NACLi_X87,
5665 NACL_EMPTY_IFLAGS, 5669 NACL_EMPTY_IFLAGS,
5666 InstFdiv, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5670 InstFdiv, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5667 /* 1230 */ 5671 /* 1231 */
5668 { NACLi_X87, 5672 { NACLi_X87,
5669 NACL_EMPTY_IFLAGS, 5673 NACL_EMPTY_IFLAGS,
5670 InstFfree, 0x00, 1, 712, NACL_OPCODE_NULL_OFFSET }, 5674 InstFfree, 0x00, 1, 712, NACL_OPCODE_NULL_OFFSET },
5671 /* 1231 */ 5675 /* 1232 */
5672 { NACLi_X87, 5676 { NACLi_X87,
5673 NACL_EMPTY_IFLAGS, 5677 NACL_EMPTY_IFLAGS,
5674 InstFfree, 0x00, 1, 713, NACL_OPCODE_NULL_OFFSET }, 5678 InstFfree, 0x00, 1, 713, NACL_OPCODE_NULL_OFFSET },
5675 /* 1232 */ 5679 /* 1233 */
5676 { NACLi_X87, 5680 { NACLi_X87,
5677 NACL_EMPTY_IFLAGS, 5681 NACL_EMPTY_IFLAGS,
5678 InstFfree, 0x00, 1, 714, NACL_OPCODE_NULL_OFFSET }, 5682 InstFfree, 0x00, 1, 714, NACL_OPCODE_NULL_OFFSET },
5679 /* 1233 */ 5683 /* 1234 */
5680 { NACLi_X87, 5684 { NACLi_X87,
5681 NACL_EMPTY_IFLAGS, 5685 NACL_EMPTY_IFLAGS,
5682 InstFfree, 0x00, 1, 715, NACL_OPCODE_NULL_OFFSET }, 5686 InstFfree, 0x00, 1, 715, NACL_OPCODE_NULL_OFFSET },
5683 /* 1234 */ 5687 /* 1235 */
5684 { NACLi_X87, 5688 { NACLi_X87,
5685 NACL_EMPTY_IFLAGS, 5689 NACL_EMPTY_IFLAGS,
5686 InstFfree, 0x00, 1, 716, NACL_OPCODE_NULL_OFFSET }, 5690 InstFfree, 0x00, 1, 716, NACL_OPCODE_NULL_OFFSET },
5687 /* 1235 */ 5691 /* 1236 */
5688 { NACLi_X87, 5692 { NACLi_X87,
5689 NACL_EMPTY_IFLAGS, 5693 NACL_EMPTY_IFLAGS,
5690 InstFfree, 0x00, 1, 717, NACL_OPCODE_NULL_OFFSET }, 5694 InstFfree, 0x00, 1, 717, NACL_OPCODE_NULL_OFFSET },
5691 /* 1236 */ 5695 /* 1237 */
5692 { NACLi_X87, 5696 { NACLi_X87,
5693 NACL_EMPTY_IFLAGS, 5697 NACL_EMPTY_IFLAGS,
5694 InstFfree, 0x00, 1, 718, NACL_OPCODE_NULL_OFFSET }, 5698 InstFfree, 0x00, 1, 718, NACL_OPCODE_NULL_OFFSET },
5695 /* 1237 */ 5699 /* 1238 */
5696 { NACLi_X87, 5700 { NACLi_X87,
5697 NACL_EMPTY_IFLAGS, 5701 NACL_EMPTY_IFLAGS,
5698 InstFfree, 0x00, 1, 719, NACL_OPCODE_NULL_OFFSET }, 5702 InstFfree, 0x00, 1, 719, NACL_OPCODE_NULL_OFFSET },
5699 /* 1238 */ 5703 /* 1239 */
5700 { NACLi_X87, 5704 { NACLi_X87,
5701 NACL_EMPTY_IFLAGS, 5705 NACL_EMPTY_IFLAGS,
5702 InstFst, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET }, 5706 InstFst, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET },
5703 /* 1239 */ 5707 /* 1240 */
5704 { NACLi_X87, 5708 { NACLi_X87,
5705 NACL_EMPTY_IFLAGS, 5709 NACL_EMPTY_IFLAGS,
5706 InstFst, 0x00, 2, 720, NACL_OPCODE_NULL_OFFSET }, 5710 InstFst, 0x00, 2, 720, NACL_OPCODE_NULL_OFFSET },
5707 /* 1240 */ 5711 /* 1241 */
5708 { NACLi_X87, 5712 { NACLi_X87,
5709 NACL_EMPTY_IFLAGS, 5713 NACL_EMPTY_IFLAGS,
5710 InstFst, 0x00, 2, 722, NACL_OPCODE_NULL_OFFSET }, 5714 InstFst, 0x00, 2, 722, NACL_OPCODE_NULL_OFFSET },
5711 /* 1241 */ 5715 /* 1242 */
5712 { NACLi_X87, 5716 { NACLi_X87,
5713 NACL_EMPTY_IFLAGS, 5717 NACL_EMPTY_IFLAGS,
5714 InstFst, 0x00, 2, 724, NACL_OPCODE_NULL_OFFSET }, 5718 InstFst, 0x00, 2, 724, NACL_OPCODE_NULL_OFFSET },
5715 /* 1242 */ 5719 /* 1243 */
5716 { NACLi_X87, 5720 { NACLi_X87,
5717 NACL_EMPTY_IFLAGS, 5721 NACL_EMPTY_IFLAGS,
5718 InstFst, 0x00, 2, 726, NACL_OPCODE_NULL_OFFSET }, 5722 InstFst, 0x00, 2, 726, NACL_OPCODE_NULL_OFFSET },
5719 /* 1243 */ 5723 /* 1244 */
5720 { NACLi_X87, 5724 { NACLi_X87,
5721 NACL_EMPTY_IFLAGS, 5725 NACL_EMPTY_IFLAGS,
5722 InstFst, 0x00, 2, 728, NACL_OPCODE_NULL_OFFSET }, 5726 InstFst, 0x00, 2, 728, NACL_OPCODE_NULL_OFFSET },
5723 /* 1244 */ 5727 /* 1245 */
5724 { NACLi_X87, 5728 { NACLi_X87,
5725 NACL_EMPTY_IFLAGS, 5729 NACL_EMPTY_IFLAGS,
5726 InstFst, 0x00, 2, 730, NACL_OPCODE_NULL_OFFSET }, 5730 InstFst, 0x00, 2, 730, NACL_OPCODE_NULL_OFFSET },
5727 /* 1245 */ 5731 /* 1246 */
5728 { NACLi_X87, 5732 { NACLi_X87,
5729 NACL_EMPTY_IFLAGS, 5733 NACL_EMPTY_IFLAGS,
5730 InstFst, 0x00, 2, 732, NACL_OPCODE_NULL_OFFSET }, 5734 InstFst, 0x00, 2, 732, NACL_OPCODE_NULL_OFFSET },
5731 /* 1246 */ 5735 /* 1247 */
5732 { NACLi_X87, 5736 { NACLi_X87,
5733 NACL_EMPTY_IFLAGS, 5737 NACL_EMPTY_IFLAGS,
5734 InstFstp, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET }, 5738 InstFstp, 0x00, 2, 666, NACL_OPCODE_NULL_OFFSET },
5735 /* 1247 */ 5739 /* 1248 */
5736 { NACLi_X87, 5740 { NACLi_X87,
5737 NACL_EMPTY_IFLAGS, 5741 NACL_EMPTY_IFLAGS,
5738 InstFstp, 0x00, 2, 720, NACL_OPCODE_NULL_OFFSET }, 5742 InstFstp, 0x00, 2, 720, NACL_OPCODE_NULL_OFFSET },
5739 /* 1248 */ 5743 /* 1249 */
5740 { NACLi_X87, 5744 { NACLi_X87,
5741 NACL_EMPTY_IFLAGS, 5745 NACL_EMPTY_IFLAGS,
5742 InstFstp, 0x00, 2, 722, NACL_OPCODE_NULL_OFFSET }, 5746 InstFstp, 0x00, 2, 722, NACL_OPCODE_NULL_OFFSET },
5743 /* 1249 */ 5747 /* 1250 */
5744 { NACLi_X87, 5748 { NACLi_X87,
5745 NACL_EMPTY_IFLAGS, 5749 NACL_EMPTY_IFLAGS,
5746 InstFstp, 0x00, 2, 724, NACL_OPCODE_NULL_OFFSET }, 5750 InstFstp, 0x00, 2, 724, NACL_OPCODE_NULL_OFFSET },
5747 /* 1250 */ 5751 /* 1251 */
5748 { NACLi_X87, 5752 { NACLi_X87,
5749 NACL_EMPTY_IFLAGS, 5753 NACL_EMPTY_IFLAGS,
5750 InstFstp, 0x00, 2, 726, NACL_OPCODE_NULL_OFFSET }, 5754 InstFstp, 0x00, 2, 726, NACL_OPCODE_NULL_OFFSET },
5751 /* 1251 */ 5755 /* 1252 */
5752 { NACLi_X87, 5756 { NACLi_X87,
5753 NACL_EMPTY_IFLAGS, 5757 NACL_EMPTY_IFLAGS,
5754 InstFstp, 0x00, 2, 728, NACL_OPCODE_NULL_OFFSET }, 5758 InstFstp, 0x00, 2, 728, NACL_OPCODE_NULL_OFFSET },
5755 /* 1252 */ 5759 /* 1253 */
5756 { NACLi_X87, 5760 { NACLi_X87,
5757 NACL_EMPTY_IFLAGS, 5761 NACL_EMPTY_IFLAGS,
5758 InstFstp, 0x00, 2, 730, NACL_OPCODE_NULL_OFFSET }, 5762 InstFstp, 0x00, 2, 730, NACL_OPCODE_NULL_OFFSET },
5759 /* 1253 */ 5763 /* 1254 */
5760 { NACLi_X87, 5764 { NACLi_X87,
5761 NACL_EMPTY_IFLAGS, 5765 NACL_EMPTY_IFLAGS,
5762 InstFstp, 0x00, 2, 732, NACL_OPCODE_NULL_OFFSET }, 5766 InstFstp, 0x00, 2, 732, NACL_OPCODE_NULL_OFFSET },
5763 /* 1254 */ 5767 /* 1255 */
5764 { NACLi_X87, 5768 { NACLi_X87,
5765 NACL_EMPTY_IFLAGS, 5769 NACL_EMPTY_IFLAGS,
5766 InstFucom, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 5770 InstFucom, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
5767 /* 1255 */ 5771 /* 1256 */
5768 { NACLi_X87, 5772 { NACLi_X87,
5769 NACL_EMPTY_IFLAGS, 5773 NACL_EMPTY_IFLAGS,
5770 InstFucom, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5774 InstFucom, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5771 /* 1256 */ 5775 /* 1257 */
5772 { NACLi_X87, 5776 { NACLi_X87,
5773 NACL_EMPTY_IFLAGS, 5777 NACL_EMPTY_IFLAGS,
5774 InstFucom, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 5778 InstFucom, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
5775 /* 1257 */ 5779 /* 1258 */
5776 { NACLi_X87, 5780 { NACLi_X87,
5777 NACL_EMPTY_IFLAGS, 5781 NACL_EMPTY_IFLAGS,
5778 InstFucom, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 5782 InstFucom, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
5779 /* 1258 */ 5783 /* 1259 */
5780 { NACLi_X87, 5784 { NACLi_X87,
5781 NACL_EMPTY_IFLAGS, 5785 NACL_EMPTY_IFLAGS,
5782 InstFucom, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 5786 InstFucom, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
5783 /* 1259 */ 5787 /* 1260 */
5784 { NACLi_X87, 5788 { NACLi_X87,
5785 NACL_EMPTY_IFLAGS, 5789 NACL_EMPTY_IFLAGS,
5786 InstFucom, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 5790 InstFucom, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
5787 /* 1260 */ 5791 /* 1261 */
5788 { NACLi_X87, 5792 { NACLi_X87,
5789 NACL_EMPTY_IFLAGS, 5793 NACL_EMPTY_IFLAGS,
5790 InstFucom, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 5794 InstFucom, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
5791 /* 1261 */ 5795 /* 1262 */
5792 { NACLi_X87, 5796 { NACLi_X87,
5793 NACL_EMPTY_IFLAGS, 5797 NACL_EMPTY_IFLAGS,
5794 InstFucom, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 5798 InstFucom, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
5795 /* 1262 */ 5799 /* 1263 */
5796 { NACLi_X87, 5800 { NACLi_X87,
5797 NACL_EMPTY_IFLAGS, 5801 NACL_EMPTY_IFLAGS,
5798 InstFucomp, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 5802 InstFucomp, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
5799 /* 1263 */ 5803 /* 1264 */
5800 { NACLi_X87, 5804 { NACLi_X87,
5801 NACL_EMPTY_IFLAGS, 5805 NACL_EMPTY_IFLAGS,
5802 InstFucomp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5806 InstFucomp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5803 /* 1264 */ 5807 /* 1265 */
5804 { NACLi_X87, 5808 { NACLi_X87,
5805 NACL_EMPTY_IFLAGS, 5809 NACL_EMPTY_IFLAGS,
5806 InstFucomp, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 5810 InstFucomp, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
5807 /* 1265 */ 5811 /* 1266 */
5808 { NACLi_X87, 5812 { NACLi_X87,
5809 NACL_EMPTY_IFLAGS, 5813 NACL_EMPTY_IFLAGS,
5810 InstFucomp, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 5814 InstFucomp, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
5811 /* 1266 */ 5815 /* 1267 */
5812 { NACLi_X87, 5816 { NACLi_X87,
5813 NACL_EMPTY_IFLAGS, 5817 NACL_EMPTY_IFLAGS,
5814 InstFucomp, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 5818 InstFucomp, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
5815 /* 1267 */ 5819 /* 1268 */
5816 { NACLi_X87, 5820 { NACLi_X87,
5817 NACL_EMPTY_IFLAGS, 5821 NACL_EMPTY_IFLAGS,
5818 InstFucomp, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 5822 InstFucomp, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
5819 /* 1268 */ 5823 /* 1269 */
5820 { NACLi_X87, 5824 { NACLi_X87,
5821 NACL_EMPTY_IFLAGS, 5825 NACL_EMPTY_IFLAGS,
5822 InstFucomp, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 5826 InstFucomp, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
5823 /* 1269 */ 5827 /* 1270 */
5824 { NACLi_X87, 5828 { NACLi_X87,
5825 NACL_EMPTY_IFLAGS, 5829 NACL_EMPTY_IFLAGS,
5826 InstFucomp, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 5830 InstFucomp, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
5827 /* 1270 */ 5831 /* 1271 */
5828 { NACLi_X87, 5832 { NACLi_X87,
5829 NACL_EMPTY_IFLAGS, 5833 NACL_EMPTY_IFLAGS,
5830 InstFaddp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5834 InstFaddp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5831 /* 1271 */ 5835 /* 1272 */
5832 { NACLi_X87, 5836 { NACLi_X87,
5833 NACL_EMPTY_IFLAGS, 5837 NACL_EMPTY_IFLAGS,
5834 InstFaddp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5838 InstFaddp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5835 /* 1272 */ 5839 /* 1273 */
5836 { NACLi_X87, 5840 { NACLi_X87,
5837 NACL_EMPTY_IFLAGS, 5841 NACL_EMPTY_IFLAGS,
5838 InstFaddp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5842 InstFaddp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5839 /* 1273 */ 5843 /* 1274 */
5840 { NACLi_X87, 5844 { NACLi_X87,
5841 NACL_EMPTY_IFLAGS, 5845 NACL_EMPTY_IFLAGS,
5842 InstFaddp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5846 InstFaddp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5843 /* 1274 */ 5847 /* 1275 */
5844 { NACLi_X87, 5848 { NACLi_X87,
5845 NACL_EMPTY_IFLAGS, 5849 NACL_EMPTY_IFLAGS,
5846 InstFaddp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5850 InstFaddp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5847 /* 1275 */ 5851 /* 1276 */
5848 { NACLi_X87, 5852 { NACLi_X87,
5849 NACL_EMPTY_IFLAGS, 5853 NACL_EMPTY_IFLAGS,
5850 InstFaddp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5854 InstFaddp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5851 /* 1276 */ 5855 /* 1277 */
5852 { NACLi_X87, 5856 { NACLi_X87,
5853 NACL_EMPTY_IFLAGS, 5857 NACL_EMPTY_IFLAGS,
5854 InstFaddp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5858 InstFaddp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5855 /* 1277 */ 5859 /* 1278 */
5856 { NACLi_X87, 5860 { NACLi_X87,
5857 NACL_EMPTY_IFLAGS, 5861 NACL_EMPTY_IFLAGS,
5858 InstFaddp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5862 InstFaddp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5859 /* 1278 */ 5863 /* 1279 */
5860 { NACLi_X87, 5864 { NACLi_X87,
5861 NACL_EMPTY_IFLAGS, 5865 NACL_EMPTY_IFLAGS,
5862 InstFmulp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5866 InstFmulp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5863 /* 1279 */ 5867 /* 1280 */
5864 { NACLi_X87, 5868 { NACLi_X87,
5865 NACL_EMPTY_IFLAGS, 5869 NACL_EMPTY_IFLAGS,
5866 InstFmulp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5870 InstFmulp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5867 /* 1280 */ 5871 /* 1281 */
5868 { NACLi_X87, 5872 { NACLi_X87,
5869 NACL_EMPTY_IFLAGS, 5873 NACL_EMPTY_IFLAGS,
5870 InstFmulp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5874 InstFmulp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5871 /* 1281 */ 5875 /* 1282 */
5872 { NACLi_X87, 5876 { NACLi_X87,
5873 NACL_EMPTY_IFLAGS, 5877 NACL_EMPTY_IFLAGS,
5874 InstFmulp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5878 InstFmulp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5875 /* 1282 */ 5879 /* 1283 */
5876 { NACLi_X87, 5880 { NACLi_X87,
5877 NACL_EMPTY_IFLAGS, 5881 NACL_EMPTY_IFLAGS,
5878 InstFmulp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5882 InstFmulp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5879 /* 1283 */ 5883 /* 1284 */
5880 { NACLi_X87, 5884 { NACLi_X87,
5881 NACL_EMPTY_IFLAGS, 5885 NACL_EMPTY_IFLAGS,
5882 InstFmulp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5886 InstFmulp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5883 /* 1284 */ 5887 /* 1285 */
5884 { NACLi_X87, 5888 { NACLi_X87,
5885 NACL_EMPTY_IFLAGS, 5889 NACL_EMPTY_IFLAGS,
5886 InstFmulp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5890 InstFmulp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5887 /* 1285 */ 5891 /* 1286 */
5888 { NACLi_X87, 5892 { NACLi_X87,
5889 NACL_EMPTY_IFLAGS, 5893 NACL_EMPTY_IFLAGS,
5890 InstFmulp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5894 InstFmulp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5891 /* 1286 */ 5895 /* 1287 */
5892 { NACLi_X87, 5896 { NACLi_X87,
5893 NACL_EMPTY_IFLAGS, 5897 NACL_EMPTY_IFLAGS,
5894 InstFcompp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 5898 InstFcompp, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
5895 /* 1287 */ 5899 /* 1288 */
5896 { NACLi_X87, 5900 { NACLi_X87,
5897 NACL_EMPTY_IFLAGS, 5901 NACL_EMPTY_IFLAGS,
5898 InstFsubrp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5902 InstFsubrp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5899 /* 1288 */ 5903 /* 1289 */
5900 { NACLi_X87, 5904 { NACLi_X87,
5901 NACL_EMPTY_IFLAGS, 5905 NACL_EMPTY_IFLAGS,
5902 InstFsubrp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5906 InstFsubrp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5903 /* 1289 */ 5907 /* 1290 */
5904 { NACLi_X87, 5908 { NACLi_X87,
5905 NACL_EMPTY_IFLAGS, 5909 NACL_EMPTY_IFLAGS,
5906 InstFsubrp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5910 InstFsubrp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5907 /* 1290 */ 5911 /* 1291 */
5908 { NACLi_X87, 5912 { NACLi_X87,
5909 NACL_EMPTY_IFLAGS, 5913 NACL_EMPTY_IFLAGS,
5910 InstFsubrp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5914 InstFsubrp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5911 /* 1291 */ 5915 /* 1292 */
5912 { NACLi_X87, 5916 { NACLi_X87,
5913 NACL_EMPTY_IFLAGS, 5917 NACL_EMPTY_IFLAGS,
5914 InstFsubrp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5918 InstFsubrp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5915 /* 1292 */ 5919 /* 1293 */
5916 { NACLi_X87, 5920 { NACLi_X87,
5917 NACL_EMPTY_IFLAGS, 5921 NACL_EMPTY_IFLAGS,
5918 InstFsubrp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5922 InstFsubrp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5919 /* 1293 */ 5923 /* 1294 */
5920 { NACLi_X87, 5924 { NACLi_X87,
5921 NACL_EMPTY_IFLAGS, 5925 NACL_EMPTY_IFLAGS,
5922 InstFsubrp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5926 InstFsubrp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5923 /* 1294 */ 5927 /* 1295 */
5924 { NACLi_X87, 5928 { NACLi_X87,
5925 NACL_EMPTY_IFLAGS, 5929 NACL_EMPTY_IFLAGS,
5926 InstFsubrp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5930 InstFsubrp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5927 /* 1295 */ 5931 /* 1296 */
5928 { NACLi_X87, 5932 { NACLi_X87,
5929 NACL_EMPTY_IFLAGS, 5933 NACL_EMPTY_IFLAGS,
5930 InstFsubp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5934 InstFsubp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5931 /* 1296 */ 5935 /* 1297 */
5932 { NACLi_X87, 5936 { NACLi_X87,
5933 NACL_EMPTY_IFLAGS, 5937 NACL_EMPTY_IFLAGS,
5934 InstFsubp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5938 InstFsubp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5935 /* 1297 */ 5939 /* 1298 */
5936 { NACLi_X87, 5940 { NACLi_X87,
5937 NACL_EMPTY_IFLAGS, 5941 NACL_EMPTY_IFLAGS,
5938 InstFsubp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5942 InstFsubp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5939 /* 1298 */ 5943 /* 1299 */
5940 { NACLi_X87, 5944 { NACLi_X87,
5941 NACL_EMPTY_IFLAGS, 5945 NACL_EMPTY_IFLAGS,
5942 InstFsubp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5946 InstFsubp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5943 /* 1299 */ 5947 /* 1300 */
5944 { NACLi_X87, 5948 { NACLi_X87,
5945 NACL_EMPTY_IFLAGS, 5949 NACL_EMPTY_IFLAGS,
5946 InstFsubp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5950 InstFsubp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5947 /* 1300 */ 5951 /* 1301 */
5948 { NACLi_X87, 5952 { NACLi_X87,
5949 NACL_EMPTY_IFLAGS, 5953 NACL_EMPTY_IFLAGS,
5950 InstFsubp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5954 InstFsubp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5951 /* 1301 */ 5955 /* 1302 */
5952 { NACLi_X87, 5956 { NACLi_X87,
5953 NACL_EMPTY_IFLAGS, 5957 NACL_EMPTY_IFLAGS,
5954 InstFsubp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5958 InstFsubp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5955 /* 1302 */ 5959 /* 1303 */
5956 { NACLi_X87, 5960 { NACLi_X87,
5957 NACL_EMPTY_IFLAGS, 5961 NACL_EMPTY_IFLAGS,
5958 InstFsubp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5962 InstFsubp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5959 /* 1303 */ 5963 /* 1304 */
5960 { NACLi_X87, 5964 { NACLi_X87,
5961 NACL_EMPTY_IFLAGS, 5965 NACL_EMPTY_IFLAGS,
5962 InstFdivrp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5966 InstFdivrp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5963 /* 1304 */ 5967 /* 1305 */
5964 { NACLi_X87, 5968 { NACLi_X87,
5965 NACL_EMPTY_IFLAGS, 5969 NACL_EMPTY_IFLAGS,
5966 InstFdivrp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 5970 InstFdivrp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5967 /* 1305 */ 5971 /* 1306 */
5968 { NACLi_X87, 5972 { NACLi_X87,
5969 NACL_EMPTY_IFLAGS, 5973 NACL_EMPTY_IFLAGS,
5970 InstFdivrp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 5974 InstFdivrp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
5971 /* 1306 */ 5975 /* 1307 */
5972 { NACLi_X87, 5976 { NACLi_X87,
5973 NACL_EMPTY_IFLAGS, 5977 NACL_EMPTY_IFLAGS,
5974 InstFdivrp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 5978 InstFdivrp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
5975 /* 1307 */ 5979 /* 1308 */
5976 { NACLi_X87, 5980 { NACLi_X87,
5977 NACL_EMPTY_IFLAGS, 5981 NACL_EMPTY_IFLAGS,
5978 InstFdivrp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 5982 InstFdivrp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
5979 /* 1308 */ 5983 /* 1309 */
5980 { NACLi_X87, 5984 { NACLi_X87,
5981 NACL_EMPTY_IFLAGS, 5985 NACL_EMPTY_IFLAGS,
5982 InstFdivrp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 5986 InstFdivrp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
5983 /* 1309 */ 5987 /* 1310 */
5984 { NACLi_X87, 5988 { NACLi_X87,
5985 NACL_EMPTY_IFLAGS, 5989 NACL_EMPTY_IFLAGS,
5986 InstFdivrp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 5990 InstFdivrp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
5987 /* 1310 */ 5991 /* 1311 */
5988 { NACLi_X87, 5992 { NACLi_X87,
5989 NACL_EMPTY_IFLAGS, 5993 NACL_EMPTY_IFLAGS,
5990 InstFdivrp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 5994 InstFdivrp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
5991 /* 1311 */ 5995 /* 1312 */
5992 { NACLi_X87, 5996 { NACLi_X87,
5993 NACL_EMPTY_IFLAGS, 5997 NACL_EMPTY_IFLAGS,
5994 InstFdivp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET }, 5998 InstFdivp, 0x00, 2, 634, NACL_OPCODE_NULL_OFFSET },
5995 /* 1312 */ 5999 /* 1313 */
5996 { NACLi_X87, 6000 { NACLi_X87,
5997 NACL_EMPTY_IFLAGS, 6001 NACL_EMPTY_IFLAGS,
5998 InstFdivp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET }, 6002 InstFdivp, 0x00, 2, 698, NACL_OPCODE_NULL_OFFSET },
5999 /* 1313 */ 6003 /* 1314 */
6000 { NACLi_X87, 6004 { NACLi_X87,
6001 NACL_EMPTY_IFLAGS, 6005 NACL_EMPTY_IFLAGS,
6002 InstFdivp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET }, 6006 InstFdivp, 0x00, 2, 700, NACL_OPCODE_NULL_OFFSET },
6003 /* 1314 */ 6007 /* 1315 */
6004 { NACLi_X87, 6008 { NACLi_X87,
6005 NACL_EMPTY_IFLAGS, 6009 NACL_EMPTY_IFLAGS,
6006 InstFdivp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET }, 6010 InstFdivp, 0x00, 2, 702, NACL_OPCODE_NULL_OFFSET },
6007 /* 1315 */ 6011 /* 1316 */
6008 { NACLi_X87, 6012 { NACLi_X87,
6009 NACL_EMPTY_IFLAGS, 6013 NACL_EMPTY_IFLAGS,
6010 InstFdivp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET }, 6014 InstFdivp, 0x00, 2, 704, NACL_OPCODE_NULL_OFFSET },
6011 /* 1316 */ 6015 /* 1317 */
6012 { NACLi_X87, 6016 { NACLi_X87,
6013 NACL_EMPTY_IFLAGS, 6017 NACL_EMPTY_IFLAGS,
6014 InstFdivp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET }, 6018 InstFdivp, 0x00, 2, 706, NACL_OPCODE_NULL_OFFSET },
6015 /* 1317 */ 6019 /* 1318 */
6016 { NACLi_X87, 6020 { NACLi_X87,
6017 NACL_EMPTY_IFLAGS, 6021 NACL_EMPTY_IFLAGS,
6018 InstFdivp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET }, 6022 InstFdivp, 0x00, 2, 708, NACL_OPCODE_NULL_OFFSET },
6019 /* 1318 */ 6023 /* 1319 */
6020 { NACLi_X87, 6024 { NACLi_X87,
6021 NACL_EMPTY_IFLAGS, 6025 NACL_EMPTY_IFLAGS,
6022 InstFdivp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET }, 6026 InstFdivp, 0x00, 2, 710, NACL_OPCODE_NULL_OFFSET },
6023 /* 1319 */ 6027 /* 1320 */
6024 { NACLi_X87, 6028 { NACLi_X87,
6025 NACL_EMPTY_IFLAGS, 6029 NACL_EMPTY_IFLAGS,
6026 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 6030 InstInvalid, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
6027 /* 1320 */ 6031 /* 1321 */
6028 { NACLi_X87, 6032 { NACLi_X87,
6029 NACL_EMPTY_IFLAGS, 6033 NACL_EMPTY_IFLAGS,
6030 InstFnstsw, 0x00, 1, 734, NACL_OPCODE_NULL_OFFSET }, 6034 InstFnstsw, 0x00, 1, 734, NACL_OPCODE_NULL_OFFSET },
6031 /* 1321 */ 6035 /* 1322 */
6032 { NACLi_X87, 6036 { NACLi_X87,
6033 NACL_EMPTY_IFLAGS, 6037 NACL_EMPTY_IFLAGS,
6034 InstFucomip, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 6038 InstFucomip, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
6035 /* 1322 */ 6039 /* 1323 */
6036 { NACLi_X87, 6040 { NACLi_X87,
6037 NACL_EMPTY_IFLAGS, 6041 NACL_EMPTY_IFLAGS,
6038 InstFucomip, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 6042 InstFucomip, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
6039 /* 1323 */ 6043 /* 1324 */
6040 { NACLi_X87, 6044 { NACLi_X87,
6041 NACL_EMPTY_IFLAGS, 6045 NACL_EMPTY_IFLAGS,
6042 InstFucomip, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 6046 InstFucomip, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
6043 /* 1324 */ 6047 /* 1325 */
6044 { NACLi_X87, 6048 { NACLi_X87,
6045 NACL_EMPTY_IFLAGS, 6049 NACL_EMPTY_IFLAGS,
6046 InstFucomip, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 6050 InstFucomip, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
6047 /* 1325 */ 6051 /* 1326 */
6048 { NACLi_X87, 6052 { NACLi_X87,
6049 NACL_EMPTY_IFLAGS, 6053 NACL_EMPTY_IFLAGS,
6050 InstFucomip, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 6054 InstFucomip, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
6051 /* 1326 */ 6055 /* 1327 */
6052 { NACLi_X87, 6056 { NACLi_X87,
6053 NACL_EMPTY_IFLAGS, 6057 NACL_EMPTY_IFLAGS,
6054 InstFucomip, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 6058 InstFucomip, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
6055 /* 1327 */ 6059 /* 1328 */
6056 { NACLi_X87, 6060 { NACLi_X87,
6057 NACL_EMPTY_IFLAGS, 6061 NACL_EMPTY_IFLAGS,
6058 InstFucomip, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 6062 InstFucomip, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
6059 /* 1328 */ 6063 /* 1329 */
6060 { NACLi_X87, 6064 { NACLi_X87,
6061 NACL_EMPTY_IFLAGS, 6065 NACL_EMPTY_IFLAGS,
6062 InstFucomip, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 6066 InstFucomip, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
6063 /* 1329 */ 6067 /* 1330 */
6064 { NACLi_X87, 6068 { NACLi_X87,
6065 NACL_EMPTY_IFLAGS, 6069 NACL_EMPTY_IFLAGS,
6066 InstFcomip, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET }, 6070 InstFcomip, 0x00, 2, 650, NACL_OPCODE_NULL_OFFSET },
6067 /* 1330 */ 6071 /* 1331 */
6068 { NACLi_X87, 6072 { NACLi_X87,
6069 NACL_EMPTY_IFLAGS, 6073 NACL_EMPTY_IFLAGS,
6070 InstFcomip, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET }, 6074 InstFcomip, 0x00, 2, 652, NACL_OPCODE_NULL_OFFSET },
6071 /* 1331 */ 6075 /* 1332 */
6072 { NACLi_X87, 6076 { NACLi_X87,
6073 NACL_EMPTY_IFLAGS, 6077 NACL_EMPTY_IFLAGS,
6074 InstFcomip, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET }, 6078 InstFcomip, 0x00, 2, 654, NACL_OPCODE_NULL_OFFSET },
6075 /* 1332 */ 6079 /* 1333 */
6076 { NACLi_X87, 6080 { NACLi_X87,
6077 NACL_EMPTY_IFLAGS, 6081 NACL_EMPTY_IFLAGS,
6078 InstFcomip, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET }, 6082 InstFcomip, 0x00, 2, 656, NACL_OPCODE_NULL_OFFSET },
6079 /* 1333 */ 6083 /* 1334 */
6080 { NACLi_X87, 6084 { NACLi_X87,
6081 NACL_EMPTY_IFLAGS, 6085 NACL_EMPTY_IFLAGS,
6082 InstFcomip, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET }, 6086 InstFcomip, 0x00, 2, 658, NACL_OPCODE_NULL_OFFSET },
6083 /* 1334 */ 6087 /* 1335 */
6084 { NACLi_X87, 6088 { NACLi_X87,
6085 NACL_EMPTY_IFLAGS, 6089 NACL_EMPTY_IFLAGS,
6086 InstFcomip, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET }, 6090 InstFcomip, 0x00, 2, 660, NACL_OPCODE_NULL_OFFSET },
6087 /* 1335 */ 6091 /* 1336 */
6088 { NACLi_X87, 6092 { NACLi_X87,
6089 NACL_EMPTY_IFLAGS, 6093 NACL_EMPTY_IFLAGS,
6090 InstFcomip, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET }, 6094 InstFcomip, 0x00, 2, 662, NACL_OPCODE_NULL_OFFSET },
6091 /* 1336 */ 6095 /* 1337 */
6092 { NACLi_X87, 6096 { NACLi_X87,
6093 NACL_EMPTY_IFLAGS, 6097 NACL_EMPTY_IFLAGS,
6094 InstFcomip, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET }, 6098 InstFcomip, 0x00, 2, 664, NACL_OPCODE_NULL_OFFSET },
6095 /* 1337 */
6096 { NACLi_386,
6097 NACL_EMPTY_IFLAGS,
6098 InstUd2, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
6099 /* 1338 */ 6099 /* 1338 */
6100 { NACLi_386, 6100 { NACLi_386,
6101 NACL_EMPTY_IFLAGS, 6101 NACL_EMPTY_IFLAGS,
6102 InstNop, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 6102 InstUd2, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
6103 /* 1339 */ 6103 /* 1339 */
6104 { NACLi_386, 6104 { NACLi_386,
6105 NACL_EMPTY_IFLAGS, 6105 NACL_EMPTY_IFLAGS,
6106 InstNop, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
6107 /* 1340 */
6108 { NACLi_386,
6109 NACL_EMPTY_IFLAGS,
6106 InstPause, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET }, 6110 InstPause, 0x00, 0, 0, NACL_OPCODE_NULL_OFFSET },
6107 }; 6111 };
6108 6112
6109 static const NaClPrefixOpcodeArrayOffset g_LookupTable[2543] = { 6113 static const NaClPrefixOpcodeArrayOffset g_LookupTable[2543] = {
6110 /* 0 */ 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 6114 /* 0 */ 1, 2, 3, 4, 5, 6, 7, 7, 8, 9,
6111 /* 10 */ 10, 11, 12, 13, 7, 7, 14, 15, 16, 17, 6115 /* 10 */ 10, 11, 12, 13, 7, 7, 14, 15, 16, 17,
6112 /* 20 */ 18, 19, 7, 7, 20, 21, 22, 23, 24, 25, 6116 /* 20 */ 18, 19, 7, 7, 20, 21, 22, 23, 24, 25,
6113 /* 30 */ 7, 7, 26, 27, 28, 29, 30, 31, 7, 7, 6117 /* 30 */ 7, 7, 26, 27, 28, 29, 30, 31, 7, 7,
6114 /* 40 */ 32, 33, 34, 35, 36, 37, 7, 7, 38, 39, 6118 /* 40 */ 32, 33, 34, 35, 36, 37, 7, 7, 38, 39,
6115 /* 50 */ 40, 41, 42, 43, 7, 7, 44, 45, 46, 47, 6119 /* 50 */ 40, 41, 42, 43, 7, 7, 44, 45, 46, 47,
(...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after
6192 /* 820 */ 729, 730, 722, 722, 722, 722, 731, 732, 733, 734, 6196 /* 820 */ 729, 730, 722, 722, 722, 722, 731, 732, 733, 734,
6193 /* 830 */ 735, 736, 737, 738, 722, 722, 722, 722, 722, 722, 6197 /* 830 */ 735, 736, 737, 738, 722, 722, 722, 722, 722, 722,
6194 /* 840 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 739, 6198 /* 840 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 739,
6195 /* 850 */ 740, 722, 722, 722, 722, 722, 722, 722, 722, 722, 6199 /* 850 */ 740, 722, 722, 722, 722, 722, 722, 722, 722, 722,
6196 /* 860 */ 722, 722, 722, 722, 741, 742, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6200 /* 860 */ 722, 722, 722, 722, 741, 742, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6197 /* 870 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6201 /* 870 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6198 /* 880 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6202 /* 880 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6199 /* 890 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6203 /* 890 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6200 /* 900 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6204 /* 900 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6201 /* 910 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6205 /* 910 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6202 /* 920 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 743, 722, 722, 7 22, 722, 744, 722, 722, 6206 /* 920 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 743, 722, 722, 7 22, 744, 745, 722, 722,
6203 /* 930 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 745, 722, 722, 7 22, 722, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, 6207 /* 930 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 746, 722, 722, 7 22, 722, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET,
6204 /* 940 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, 722, 722, 722, 722, 6208 /* 940 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, 722, 722, 722, 722,
6205 /* 950 */ 722, 722, 746, 722, 722, 722, 722, 722, 722, 722, 6209 /* 950 */ 722, 722, 747, 722, 722, 722, 722, 722, 722, 722,
6206 /* 960 */ 722, 722, 722, 722, 722, 722, 722, 722, 747, 722, 6210 /* 960 */ 722, 722, 722, 722, 722, 722, 722, 722, 748, 722,
6207 /* 970 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 6211 /* 970 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 722,
6208 /* 980 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 6212 /* 980 */ 722, 722, 722, 722, 722, 722, 722, 722, 722, 722,
6209 /* 990 */ 722, 722, 722, 722, NACL_OPCODE_NULL_OFFSET, 748, 749, 750, 751, 7 52, 6213 /* 990 */ 722, 722, 722, 722, NACL_OPCODE_NULL_OFFSET, 749, 750, 751, 752, 7 53,
6210 /* 1000 */ 753, 754, 755, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6214 /* 1000 */ 754, 755, 756, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6211 /* 1010 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 56, 6215 /* 1010 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 57,
6212 /* 1020 */ 757, 758, 759, 760, 761, 762, 763, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6216 /* 1020 */ 758, 759, 760, 761, 762, 763, 764, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6213 /* 1030 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6217 /* 1030 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6214 /* 1040 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6218 /* 1040 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6215 /* 1050 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 64, 6219 /* 1050 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 65,
6216 /* 1060 */ 765, 766, 766, 767, 768, 769, 770, 771, 772, 773, 6220 /* 1060 */ 766, 767, 767, 768, 769, 770, 771, 772, 773, 774,
6217 /* 1070 */ 774, 775, 776, 777, 778, 779, 780, 781, 782, 783, 6221 /* 1070 */ 775, 776, 777, 778, 779, 780, 781, 782, 783, 784,
6218 /* 1080 */ 784, 785, 786, 787, 788, 789, 790, 791, 792, 794, 6222 /* 1080 */ 785, 786, 787, 788, 789, 790, 791, 792, 793, 795,
6219 /* 1090 */ 795, 796, 804, 811, 819, 820, 821, 822, 766, 824, 6223 /* 1090 */ 796, 797, 805, 812, 820, 821, 822, 823, 767, 825,
6220 /* 1100 */ 825, 766, 766, 826, 827, 829, 830, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6224 /* 1100 */ 826, 767, 767, 827, 828, 830, 831, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6221 /* 1110 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6225 /* 1110 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6222 /* 1120 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6226 /* 1120 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6223 /* 1130 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6227 /* 1130 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6224 /* 1140 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6228 /* 1140 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6225 /* 1150 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 766, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, 6229 /* 1150 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 767, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET,
6226 /* 1160 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6230 /* 1160 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6227 /* 1170 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 831, 766, 832, 833, 834, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, 6231 /* 1170 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 832, 767, 833, 834, 835, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET,
6228 /* 1180 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, 835, 836, 837, 6232 /* 1180 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, 836, 837, 838,
6229 /* 1190 */ 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 6233 /* 1190 */ 839, 840, 841, 842, 843, 844, 845, 846, 847, 848,
6230 /* 1200 */ 848, 849, 850, 851, 852, 853, 854, 855, 856, 857, 6234 /* 1200 */ 849, 850, 851, 852, 853, 854, 855, 856, 857, 858,
6231 /* 1210 */ 858, 859, 860, 861, 862, 863, 864, 865, 866, 766, 6235 /* 1210 */ 859, 860, 861, 862, 863, 864, 865, 866, 867, 767,
6232 /* 1220 */ 867, 868, 869, 870, 871, 872, 873, 874, 875, 876, 6236 /* 1220 */ 868, 869, 870, 871, 872, 873, 874, 875, 876, 877,
6233 /* 1230 */ 877, 878, 879, 880, 766, NACL_OPCODE_NULL_OFFSET, 881, 882, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6237 /* 1230 */ 878, 879, 880, 881, 767, NACL_OPCODE_NULL_OFFSET, 882, 883, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6234 /* 1240 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6238 /* 1240 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6235 /* 1250 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 883, 884, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6239 /* 1250 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 884, 885, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6236 /* 1260 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6240 /* 1260 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6237 /* 1270 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6241 /* 1270 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6238 /* 1280 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6242 /* 1280 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6239 /* 1290 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6243 /* 1290 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6240 /* 1300 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6244 /* 1300 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6241 /* 1310 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6245 /* 1310 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6242 /* 1320 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6246 /* 1320 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6243 /* 1330 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6247 /* 1330 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6244 /* 1340 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6248 /* 1340 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6245 /* 1350 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6249 /* 1350 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6246 /* 1360 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 885, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 886, NACL_OPCODE _NULL_OFFSET, 887, NACL_OPCODE_NULL_OFFSET, 6250 /* 1360 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 886, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 887, NACL_OPCODE _NULL_OFFSET, 888, NACL_OPCODE_NULL_OFFSET,
6247 /* 1370 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 888, NACL_OPCODE _NULL_OFFSET, 889, 890, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 891, N ACL_OPCODE_NULL_OFFSET, 6251 /* 1370 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 889, NACL_OPCODE _NULL_OFFSET, 890, 891, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 892, N ACL_OPCODE_NULL_OFFSET,
6248 /* 1380 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 892, NACL_OPCODE _NULL_OFFSET, 893, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, 894, NACL_OPCODE_NULL_OFFSET, 6252 /* 1380 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 893, NACL_OPCODE _NULL_OFFSET, 894, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, 895, NACL_OPCODE_NULL_OFFSET,
6249 /* 1390 */ 895, 896, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 897, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 898, N ACL_OPCODE_NULL_OFFSET, 6253 /* 1390 */ 896, 897, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 898, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 899, N ACL_OPCODE_NULL_OFFSET,
6250 /* 1400 */ 899, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, 900, NACL_OPCODE_NULL_OFFSET, 901, 902, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6254 /* 1400 */ 900, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, 901, NACL_OPCODE_NULL_OFFSET, 902, 903, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6251 /* 1410 */ NACL_OPCODE_NULL_OFFSET, 903, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 904, NACL_OPCODE_NULL_OFFSET, 905, 906, 9 07, 6255 /* 1410 */ NACL_OPCODE_NULL_OFFSET, 904, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE _NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 905, NACL_OPCODE_NULL_OFFSET, 906, 907, 9 08,
6252 /* 1420 */ 908, 909, 910, 911, 912, 913, 914, 915, 916, 7, 6256 /* 1420 */ 909, 910, 911, 912, 913, 914, 915, 916, 917, 7,
6253 /* 1430 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6257 /* 1430 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6254 /* 1440 */ 7, 7, 7, 7, 7, 917, 918, 919, 7, 7, 6258 /* 1440 */ 7, 7, 7, 7, 7, 918, 919, 920, 7, 7,
6255 /* 1450 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6259 /* 1450 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6256 /* 1460 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6260 /* 1460 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6257 /* 1470 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6261 /* 1470 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6258 /* 1480 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6262 /* 1480 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6259 /* 1490 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6263 /* 1490 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6260 /* 1500 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6264 /* 1500 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6261 /* 1510 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6265 /* 1510 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6262 /* 1520 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6266 /* 1520 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6263 /* 1530 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6267 /* 1530 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6264 /* 1540 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6268 /* 1540 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6265 /* 1550 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6269 /* 1550 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6266 /* 1560 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6270 /* 1560 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6267 /* 1570 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6271 /* 1570 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6268 /* 1580 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6272 /* 1580 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6269 /* 1590 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6273 /* 1590 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6270 /* 1600 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6274 /* 1600 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6271 /* 1610 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6275 /* 1610 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6272 /* 1620 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6276 /* 1620 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6273 /* 1630 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6277 /* 1630 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6274 /* 1640 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6278 /* 1640 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6275 /* 1650 */ 7, 7, 7, 7, 7, 7, 7, 920, 921, 7, 6279 /* 1650 */ 7, 7, 7, 7, 7, 7, 7, 921, 922, 7,
6276 /* 1660 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6280 /* 1660 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6277 /* 1670 */ 7, 7, 7, 922, 923, 924, 925, 926, 927, 928, 6281 /* 1670 */ 7, 7, 7, 923, 924, 925, 926, 927, 928, 929,
6278 /* 1680 */ 929, 930, 931, 932, 933, 766, 766, 766, 766, 934, 6282 /* 1680 */ 930, 931, 932, 933, 934, 767, 767, 767, 767, 935,
6279 /* 1690 */ 766, 766, 766, 935, 936, 766, 937, 766, 766, 766, 6283 /* 1690 */ 767, 767, 767, 936, 937, 767, 938, 767, 767, 767,
6280 /* 1700 */ 766, 938, 939, 940, 766, 941, 942, 943, 944, 945, 6284 /* 1700 */ 767, 939, 940, 941, 767, 942, 943, 944, 945, 946,
6281 /* 1710 */ 946, 766, 766, 947, 948, 949, 950, 766, 766, 766, 6285 /* 1710 */ 947, 767, 767, 948, 949, 950, 951, 767, 767, 767,
6282 /* 1720 */ 766, 951, 952, 953, 954, 955, 956, 766, 957, 958, 6286 /* 1720 */ 767, 952, 953, 954, 955, 956, 957, 767, 958, 959,
6283 /* 1730 */ 959, 960, 961, 962, 963, 964, 965, 966, 967, 766, 6287 /* 1730 */ 960, 961, 962, 963, 964, 965, 966, 967, 968, 767,
6284 /* 1740 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6288 /* 1740 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6285 /* 1750 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6289 /* 1750 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6286 /* 1760 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6290 /* 1760 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6287 /* 1770 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6291 /* 1770 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6288 /* 1780 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6292 /* 1780 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6289 /* 1790 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6293 /* 1790 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6290 /* 1800 */ 766, 968, 969, 766, 766, 766, 766, 766, 766, 766, 6294 /* 1800 */ 767, 969, 970, 767, 767, 767, 767, 767, 767, 767,
6291 /* 1810 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6295 /* 1810 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6292 /* 1820 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6296 /* 1820 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6293 /* 1830 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6297 /* 1830 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6294 /* 1840 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6298 /* 1840 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6295 /* 1850 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6299 /* 1850 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6296 /* 1860 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6300 /* 1860 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6297 /* 1870 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6301 /* 1870 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6298 /* 1880 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6302 /* 1880 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6299 /* 1890 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6303 /* 1890 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6300 /* 1900 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, 766, 6304 /* 1900 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, 767,
6301 /* 1910 */ 766, 766, 766, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 66, 766, 766, 766, 766, 6305 /* 1910 */ 767, 767, 767, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 7 67, 767, 767, 767, 767,
6302 /* 1920 */ 766, 766, 766, 766, 766, 766, 766, 766, 766, NACL_OPCODE_NULL_OFFS ET, 6306 /* 1920 */ 767, 767, 767, 767, 767, 767, 767, 767, 767, NACL_OPCODE_NULL_OFFS ET,
6303 /* 1930 */ 970, 971, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 972, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 973, 974, 975, 6307 /* 1930 */ 971, 972, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 973, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 974, 975, 976,
6304 /* 1940 */ 976, 977, 978, 979, 980, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 981, 6308 /* 1940 */ 977, 978, 979, 980, 981, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 982,
6305 /* 1950 */ 982, 984, 985, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6309 /* 1950 */ 983, 985, 986, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6306 /* 1960 */ NACL_OPCODE_NULL_OFFSET, 986, 987, 989, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6310 /* 1960 */ NACL_OPCODE_NULL_OFFSET, 987, 988, 990, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6307 /* 1970 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6311 /* 1970 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6308 /* 1980 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6312 /* 1980 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6309 /* 1990 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 990, 991, 992, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 6313 /* 1990 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, 991, 992, 993, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_O PCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET,
6310 /* 2000 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6314 /* 2000 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6311 /* 2010 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET, 6315 /* 2010 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFS ET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, N ACL_OPCODE_NULL_OFFSET,
6312 /* 2020 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 993, 994, 995, 996, N ACL_OPCODE_NULL_OFFSET, 6316 /* 2020 */ NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL _OFFSET, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 994, 995, 996, 997, N ACL_OPCODE_NULL_OFFSET,
6313 /* 2030 */ NACL_OPCODE_NULL_OFFSET, 997, 998, 999, 1000, 1001, 1002, 1003, 10 04, 1005, 6317 /* 2030 */ NACL_OPCODE_NULL_OFFSET, 998, 999, 1000, 1001, 1002, 1003, 1004, 1 005, 1006,
6314 /* 2040 */ 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 6318 /* 2040 */ 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016,
6315 /* 2050 */ 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, 1024, 1025, 6319 /* 2050 */ 1017, 1018, 1019, 1020, 1021, 1022, 1023, 1024, 1025, 1026,
6316 /* 2060 */ 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 6320 /* 2060 */ 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036,
6317 /* 2070 */ 1036, 1037, 1038, 1039, 1040, 1041, 1042, 1043, 1044, 1045, 6321 /* 2070 */ 1037, 1038, 1039, 1040, 1041, 1042, 1043, 1044, 1045, 1046,
6318 /* 2080 */ 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, 6322 /* 2080 */ 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, 1056,
6319 /* 2090 */ 1056, 1057, 1058, 1059, 1060, NACL_OPCODE_NULL_OFFSET, 1061, 1062, 1063, 1064, 6323 /* 2090 */ 1057, 1058, 1059, 1060, 1061, NACL_OPCODE_NULL_OFFSET, 1062, 1063, 1064, 1065,
6320 /* 2100 */ 1065, 1066, 1067, 1068, 1069, 1070, 1071, 1072, 1073, 1074, 6324 /* 2100 */ 1066, 1067, 1068, 1069, 1070, 1071, 1072, 1073, 1074, 1075,
6321 /* 2110 */ 1075, 1076, 1077, 7, 7, 7, 7, 7, 7, 7, 6325 /* 2110 */ 1076, 1077, 1078, 7, 7, 7, 7, 7, 7, 7,
6322 /* 2120 */ 7, 7, 7, 7, 7, 7, 7, 7, 1078, 1079, 6326 /* 2120 */ 7, 7, 7, 7, 7, 7, 7, 7, 1079, 1080,
6323 /* 2130 */ 7, 7, 1080, 1081, 7, 7, 1082, 1083, 1084, 1085, 6327 /* 2130 */ 7, 7, 1081, 1082, 7, 7, 1083, 1084, 1085, 1086,
6324 /* 2140 */ 1086, 1087, 1088, 7, 1089, 1090, 1091, 1092, 1093, 1094, 6328 /* 2140 */ 1087, 1088, 1089, 7, 1090, 1091, 1092, 1093, 1094, 1095,
6325 /* 2150 */ 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, 1104, 6329 /* 2150 */ 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, 1104, 1105,
6326 /* 2160 */ NACL_OPCODE_NULL_OFFSET, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 6330 /* 2160 */ NACL_OPCODE_NULL_OFFSET, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114,
6327 /* 2170 */ 1114, 1115, 1116, 1117, 1118, 1119, 1120, 1121, 1122, 1123, 6331 /* 2170 */ 1115, 1116, 1117, 1118, 1119, 1120, 1121, 1122, 1123, 1124,
6328 /* 2180 */ 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 6332 /* 2180 */ 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134,
6329 /* 2190 */ 1134, 1135, 1136, 7, 7, 7, 7, 7, 7, 7, 6333 /* 2190 */ 1135, 1136, 1137, 7, 7, 7, 7, 7, 7, 7,
6330 /* 2200 */ 7, 7, 1137, 7, 7, 7, 7, 7, 7, 7, 6334 /* 2200 */ 7, 7, 1138, 7, 7, 7, 7, 7, 7, 7,
6331 /* 2210 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6335 /* 2210 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6332 /* 2220 */ 7, 7, 7, 7, 7, NACL_OPCODE_NULL_OFFSET, 1138, 1139, 1140, 1141, 6336 /* 2220 */ 7, 7, 7, 7, 7, NACL_OPCODE_NULL_OFFSET, 1139, 1140, 1141, 1142,
6333 /* 2230 */ 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, 6337 /* 2230 */ 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, 1152,
6334 /* 2240 */ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 6338 /* 2240 */ 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162,
6335 /* 2250 */ 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 7, 7, 6339 /* 2250 */ 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 7, 7,
6336 /* 2260 */ 1170, 1171, 7, 7, 7, 7, 1172, 1173, 1174, 1175, 6340 /* 2260 */ 1171, 1172, 7, 7, 7, 7, 1173, 1174, 1175, 1176,
6337 /* 2270 */ 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 6341 /* 2270 */ 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186,
6338 /* 2280 */ 1186, 1187, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 997, 1188, 1189, 1190, 1191, 1192, 6342 /* 2280 */ 1187, 1188, NACL_OPCODE_NULL_OFFSET, NACL_OPCODE_NULL_OFFSET, 998, 1189, 1190, 1191, 1192, 1193,
6339 /* 2290 */ 1193, 1194, 1005, 1195, 1196, 1197, 1198, 1199, 1200, 1201, 6343 /* 2290 */ 1194, 1195, 1006, 1196, 1197, 1198, 1199, 1200, 1201, 1202,
6340 /* 2300 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6344 /* 2300 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6341 /* 2310 */ 7, 7, 7, 7, 7, 7, 1037, 1202, 1203, 1204, 6345 /* 2310 */ 7, 7, 7, 7, 7, 7, 1038, 1203, 1204, 1205,
6342 /* 2320 */ 1205, 1206, 1207, 1208, 1029, 1209, 1210, 1211, 1212, 1213, 6346 /* 2320 */ 1206, 1207, 1208, 1209, 1030, 1210, 1211, 1212, 1213, 1214,
6343 /* 2330 */ 1214, 1215, 1053, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 6347 /* 2330 */ 1215, 1216, 1054, 1217, 1218, 1219, 1220, 1221, 1222, 1223,
6344 /* 2340 */ 1045, 1223, 1224, 1225, 1226, 1227, 1228, 1229, NACL_OPCODE_NULL_O FFSET, 1230, 6348 /* 2340 */ 1046, 1224, 1225, 1226, 1227, 1228, 1229, 1230, NACL_OPCODE_NULL_O FFSET, 1231,
6345 /* 2350 */ 1231, 1232, 1233, 1234, 1235, 1236, 1237, 7, 7, 7, 6349 /* 2350 */ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 7, 7, 7,
6346 /* 2360 */ 7, 7, 7, 7, 7, 1238, 1239, 1240, 1241, 1242, 6350 /* 2360 */ 7, 7, 7, 7, 7, 1239, 1240, 1241, 1242, 1243,
6347 /* 2370 */ 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 6351 /* 2370 */ 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1253,
6348 /* 2380 */ 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 6352 /* 2380 */ 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
6349 /* 2390 */ 1263, 1264, 1265, 1266, 1267, 1268, 1269, 7, 7, 7, 6353 /* 2390 */ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 7, 7, 7,
6350 /* 2400 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6354 /* 2400 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
6351 /* 2410 */ 7, 7, 7, NACL_OPCODE_NULL_OFFSET, 1270, 1271, 1272, 1273, 1274, 12 75, 6355 /* 2410 */ 7, 7, 7, NACL_OPCODE_NULL_OFFSET, 1271, 1272, 1273, 1274, 1275, 12 76,
6352 /* 2420 */ 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 6356 /* 2420 */ 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286,
6353 /* 2430 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 1286, 6357 /* 2430 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 1287,
6354 /* 2440 */ 7, 7, 7, 7, 7, 7, 1287, 1288, 1289, 1290, 6358 /* 2440 */ 7, 7, 7, 7, 7, 7, 1288, 1289, 1290, 1291,
6355 /* 2450 */ 1291, 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 6359 /* 2450 */ 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301,
6356 /* 2460 */ 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 6360 /* 2460 */ 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
6357 /* 2470 */ 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, NACL_OPCODE_NULL_O FFSET, 1319, 6361 /* 2470 */ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, NACL_OPCODE_NULL_O FFSET, 1320,
6358 /* 2480 */ 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 6362 /* 2480 */ 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320,
6359 /* 2490 */ 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 6363 /* 2490 */ 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320,
6360 /* 2500 */ 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 1319, 6364 /* 2500 */ 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320,
6361 /* 2510 */ 1319, 1320, 7, 7, 7, 7, 7, 7, 7, 1321, 6365 /* 2510 */ 1320, 1321, 7, 7, 7, 7, 7, 7, 7, 1322,
6362 /* 2520 */ 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 6366 /* 2520 */ 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332,
6363 /* 2530 */ 1332, 1333, 1334, 1335, 1336, 7, 7, 7, 7, 7, 6367 /* 2530 */ 1333, 1334, 1335, 1336, 1337, 7, 7, 7, 7, 7,
6364 /* 2540 */ 7, 7, 7, }; 6368 /* 2540 */ 7, 7, 7, };
6365 6369
6366 static const NaClPrefixOpcodeSelector g_PrefixOpcode[NaClInstPrefixEnumSize] = { 6370 static const NaClPrefixOpcodeSelector g_PrefixOpcode[NaClInstPrefixEnumSize] = {
6367 /* NoPrefix */ { 0 , 0x00, 0xff }, 6371 /* NoPrefix */ { 0 , 0x00, 0xff },
6368 /* Prefix0F */ { 256 , 0x00, 0xff }, 6372 /* Prefix0F */ { 256 , 0x00, 0xff },
6369 /* PrefixF20F */ { 512 , 0x0f, 0xff }, 6373 /* PrefixF20F */ { 512 , 0x0f, 0xff },
6370 /* PrefixF30F */ { 753 , 0x0f, 0xff }, 6374 /* PrefixF30F */ { 753 , 0x0f, 0xff },
6371 /* Prefix660F */ { 994 , 0x0f, 0xff }, 6375 /* Prefix660F */ { 994 , 0x0f, 0xff },
6372 /* Prefix0F0F */ { 1235 , 0x0b, 0xc0 }, 6376 /* Prefix0F0F */ { 1235 , 0x0b, 0xc0 },
6373 /* Prefix0F38 */ { 1417 , 0x00, 0xff }, 6377 /* Prefix0F38 */ { 1417 , 0x00, 0xff },
(...skipping 48 matching lines...) Expand 10 before | Expand all | Expand 10 after
6422 6426
6423 static const NaClInstNode g_OpcodeSeq[95] = { 6427 static const NaClInstNode g_OpcodeSeq[95] = {
6424 /* 0 */ 6428 /* 0 */
6425 { 0x0f, 6429 { 0x0f,
6426 NACL_OPCODE_NULL_OFFSET, 6430 NACL_OPCODE_NULL_OFFSET,
6427 g_OpcodeSeq + 1, 6431 g_OpcodeSeq + 1,
6428 g_OpcodeSeq + 20, 6432 g_OpcodeSeq + 20,
6429 }, 6433 },
6430 /* 1 */ 6434 /* 1 */
6431 { 0x0b, 6435 { 0x0b,
6432 1337, 6436 1338,
6433 NULL, 6437 NULL,
6434 g_OpcodeSeq + 2, 6438 g_OpcodeSeq + 2,
6435 }, 6439 },
6436 /* 2 */ 6440 /* 2 */
6437 { 0x1f, 6441 { 0x1f,
6438 NACL_OPCODE_NULL_OFFSET, 6442 NACL_OPCODE_NULL_OFFSET,
6439 g_OpcodeSeq + 3, 6443 g_OpcodeSeq + 3,
6440 NULL, 6444 NULL,
6441 }, 6445 },
6442 /* 3 */ 6446 /* 3 */
6443 { 0x00, 6447 { 0x00,
6444 1338, 6448 1339,
6445 NULL, 6449 NULL,
6446 g_OpcodeSeq + 4, 6450 g_OpcodeSeq + 4,
6447 }, 6451 },
6448 /* 4 */ 6452 /* 4 */
6449 { 0x40, 6453 { 0x40,
6450 NACL_OPCODE_NULL_OFFSET, 6454 NACL_OPCODE_NULL_OFFSET,
6451 g_OpcodeSeq + 5, 6455 g_OpcodeSeq + 5,
6452 g_OpcodeSeq + 6, 6456 g_OpcodeSeq + 6,
6453 }, 6457 },
6454 /* 5 */ 6458 /* 5 */
6455 { 0x00, 6459 { 0x00,
6456 1338, 6460 1339,
6457 NULL, 6461 NULL,
6458 NULL, 6462 NULL,
6459 }, 6463 },
6460 /* 6 */ 6464 /* 6 */
6461 { 0x44, 6465 { 0x44,
6462 NACL_OPCODE_NULL_OFFSET, 6466 NACL_OPCODE_NULL_OFFSET,
6463 g_OpcodeSeq + 7, 6467 g_OpcodeSeq + 7,
6464 g_OpcodeSeq + 9, 6468 g_OpcodeSeq + 9,
6465 }, 6469 },
6466 /* 7 */ 6470 /* 7 */
6467 { 0x00, 6471 { 0x00,
6468 NACL_OPCODE_NULL_OFFSET, 6472 NACL_OPCODE_NULL_OFFSET,
6469 g_OpcodeSeq + 8, 6473 g_OpcodeSeq + 8,
6470 NULL, 6474 NULL,
6471 }, 6475 },
6472 /* 8 */ 6476 /* 8 */
6473 { 0x00, 6477 { 0x00,
6474 1338, 6478 1339,
6475 NULL, 6479 NULL,
6476 NULL, 6480 NULL,
6477 }, 6481 },
6478 /* 9 */ 6482 /* 9 */
6479 { 0x80, 6483 { 0x80,
6480 NACL_OPCODE_NULL_OFFSET, 6484 NACL_OPCODE_NULL_OFFSET,
6481 g_OpcodeSeq + 10, 6485 g_OpcodeSeq + 10,
6482 g_OpcodeSeq + 14, 6486 g_OpcodeSeq + 14,
6483 }, 6487 },
6484 /* 10 */ 6488 /* 10 */
6485 { 0x00, 6489 { 0x00,
6486 NACL_OPCODE_NULL_OFFSET, 6490 NACL_OPCODE_NULL_OFFSET,
6487 g_OpcodeSeq + 11, 6491 g_OpcodeSeq + 11,
6488 NULL, 6492 NULL,
6489 }, 6493 },
6490 /* 11 */ 6494 /* 11 */
6491 { 0x00, 6495 { 0x00,
6492 NACL_OPCODE_NULL_OFFSET, 6496 NACL_OPCODE_NULL_OFFSET,
6493 g_OpcodeSeq + 12, 6497 g_OpcodeSeq + 12,
6494 NULL, 6498 NULL,
6495 }, 6499 },
6496 /* 12 */ 6500 /* 12 */
6497 { 0x00, 6501 { 0x00,
6498 NACL_OPCODE_NULL_OFFSET, 6502 NACL_OPCODE_NULL_OFFSET,
6499 g_OpcodeSeq + 13, 6503 g_OpcodeSeq + 13,
6500 NULL, 6504 NULL,
6501 }, 6505 },
6502 /* 13 */ 6506 /* 13 */
6503 { 0x00, 6507 { 0x00,
6504 1338, 6508 1339,
6505 NULL, 6509 NULL,
6506 NULL, 6510 NULL,
6507 }, 6511 },
6508 /* 14 */ 6512 /* 14 */
6509 { 0x84, 6513 { 0x84,
6510 NACL_OPCODE_NULL_OFFSET, 6514 NACL_OPCODE_NULL_OFFSET,
6511 g_OpcodeSeq + 15, 6515 g_OpcodeSeq + 15,
6512 NULL, 6516 NULL,
6513 }, 6517 },
6514 /* 15 */ 6518 /* 15 */
(...skipping 15 matching lines...) Expand all
6530 NULL, 6534 NULL,
6531 }, 6535 },
6532 /* 18 */ 6536 /* 18 */
6533 { 0x00, 6537 { 0x00,
6534 NACL_OPCODE_NULL_OFFSET, 6538 NACL_OPCODE_NULL_OFFSET,
6535 g_OpcodeSeq + 19, 6539 g_OpcodeSeq + 19,
6536 NULL, 6540 NULL,
6537 }, 6541 },
6538 /* 19 */ 6542 /* 19 */
6539 { 0x00, 6543 { 0x00,
6540 1338, 6544 1339,
6541 NULL, 6545 NULL,
6542 NULL, 6546 NULL,
6543 }, 6547 },
6544 /* 20 */ 6548 /* 20 */
6545 { 0x66, 6549 { 0x66,
6546 NACL_OPCODE_NULL_OFFSET, 6550 NACL_OPCODE_NULL_OFFSET,
6547 g_OpcodeSeq + 21, 6551 g_OpcodeSeq + 21,
6548 g_OpcodeSeq + 92, 6552 g_OpcodeSeq + 92,
6549 }, 6553 },
6550 /* 21 */ 6554 /* 21 */
(...skipping 15 matching lines...) Expand all
6566 g_OpcodeSeq + 26, 6570 g_OpcodeSeq + 26,
6567 }, 6571 },
6568 /* 24 */ 6572 /* 24 */
6569 { 0x00, 6573 { 0x00,
6570 NACL_OPCODE_NULL_OFFSET, 6574 NACL_OPCODE_NULL_OFFSET,
6571 g_OpcodeSeq + 25, 6575 g_OpcodeSeq + 25,
6572 NULL, 6576 NULL,
6573 }, 6577 },
6574 /* 25 */ 6578 /* 25 */
6575 { 0x00, 6579 { 0x00,
6576 1338, 6580 1339,
6577 NULL, 6581 NULL,
6578 NULL, 6582 NULL,
6579 }, 6583 },
6580 /* 26 */ 6584 /* 26 */
6581 { 0x84, 6585 { 0x84,
6582 NACL_OPCODE_NULL_OFFSET, 6586 NACL_OPCODE_NULL_OFFSET,
6583 g_OpcodeSeq + 27, 6587 g_OpcodeSeq + 27,
6584 NULL, 6588 NULL,
6585 }, 6589 },
6586 /* 27 */ 6590 /* 27 */
(...skipping 15 matching lines...) Expand all
6602 NULL, 6606 NULL,
6603 }, 6607 },
6604 /* 30 */ 6608 /* 30 */
6605 { 0x00, 6609 { 0x00,
6606 NACL_OPCODE_NULL_OFFSET, 6610 NACL_OPCODE_NULL_OFFSET,
6607 g_OpcodeSeq + 31, 6611 g_OpcodeSeq + 31,
6608 NULL, 6612 NULL,
6609 }, 6613 },
6610 /* 31 */ 6614 /* 31 */
6611 { 0x00, 6615 { 0x00,
6612 1338, 6616 1339,
6613 NULL, 6617 NULL,
6614 NULL, 6618 NULL,
6615 }, 6619 },
6616 /* 32 */ 6620 /* 32 */
6617 { 0x2e, 6621 { 0x2e,
6618 NACL_OPCODE_NULL_OFFSET, 6622 NACL_OPCODE_NULL_OFFSET,
6619 g_OpcodeSeq + 33, 6623 g_OpcodeSeq + 33,
6620 g_OpcodeSeq + 41, 6624 g_OpcodeSeq + 41,
6621 }, 6625 },
6622 /* 33 */ 6626 /* 33 */
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
6656 NULL, 6660 NULL,
6657 }, 6661 },
6658 /* 39 */ 6662 /* 39 */
6659 { 0x00, 6663 { 0x00,
6660 NACL_OPCODE_NULL_OFFSET, 6664 NACL_OPCODE_NULL_OFFSET,
6661 g_OpcodeSeq + 40, 6665 g_OpcodeSeq + 40,
6662 NULL, 6666 NULL,
6663 }, 6667 },
6664 /* 40 */ 6668 /* 40 */
6665 { 0x00, 6669 { 0x00,
6666 1338, 6670 1339,
6667 NULL, 6671 NULL,
6668 NULL, 6672 NULL,
6669 }, 6673 },
6670 /* 41 */ 6674 /* 41 */
6671 { 0x66, 6675 { 0x66,
6672 NACL_OPCODE_NULL_OFFSET, 6676 NACL_OPCODE_NULL_OFFSET,
6673 g_OpcodeSeq + 42, 6677 g_OpcodeSeq + 42,
6674 g_OpcodeSeq + 91, 6678 g_OpcodeSeq + 91,
6675 }, 6679 },
6676 /* 42 */ 6680 /* 42 */
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
6716 NULL, 6720 NULL,
6717 }, 6721 },
6718 /* 49 */ 6722 /* 49 */
6719 { 0x00, 6723 { 0x00,
6720 NACL_OPCODE_NULL_OFFSET, 6724 NACL_OPCODE_NULL_OFFSET,
6721 g_OpcodeSeq + 50, 6725 g_OpcodeSeq + 50,
6722 NULL, 6726 NULL,
6723 }, 6727 },
6724 /* 50 */ 6728 /* 50 */
6725 { 0x00, 6729 { 0x00,
6726 1338, 6730 1339,
6727 NULL, 6731 NULL,
6728 NULL, 6732 NULL,
6729 }, 6733 },
6730 /* 51 */ 6734 /* 51 */
6731 { 0x66, 6735 { 0x66,
6732 NACL_OPCODE_NULL_OFFSET, 6736 NACL_OPCODE_NULL_OFFSET,
6733 g_OpcodeSeq + 52, 6737 g_OpcodeSeq + 52,
6734 NULL, 6738 NULL,
6735 }, 6739 },
6736 /* 52 */ 6740 /* 52 */
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
6776 NULL, 6780 NULL,
6777 }, 6781 },
6778 /* 59 */ 6782 /* 59 */
6779 { 0x00, 6783 { 0x00,
6780 NACL_OPCODE_NULL_OFFSET, 6784 NACL_OPCODE_NULL_OFFSET,
6781 g_OpcodeSeq + 60, 6785 g_OpcodeSeq + 60,
6782 NULL, 6786 NULL,
6783 }, 6787 },
6784 /* 60 */ 6788 /* 60 */
6785 { 0x00, 6789 { 0x00,
6786 1338, 6790 1339,
6787 NULL, 6791 NULL,
6788 NULL, 6792 NULL,
6789 }, 6793 },
6790 /* 61 */ 6794 /* 61 */
6791 { 0x66, 6795 { 0x66,
6792 NACL_OPCODE_NULL_OFFSET, 6796 NACL_OPCODE_NULL_OFFSET,
6793 g_OpcodeSeq + 62, 6797 g_OpcodeSeq + 62,
6794 NULL, 6798 NULL,
6795 }, 6799 },
6796 /* 62 */ 6800 /* 62 */
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
6836 NULL, 6840 NULL,
6837 }, 6841 },
6838 /* 69 */ 6842 /* 69 */
6839 { 0x00, 6843 { 0x00,
6840 NACL_OPCODE_NULL_OFFSET, 6844 NACL_OPCODE_NULL_OFFSET,
6841 g_OpcodeSeq + 70, 6845 g_OpcodeSeq + 70,
6842 NULL, 6846 NULL,
6843 }, 6847 },
6844 /* 70 */ 6848 /* 70 */
6845 { 0x00, 6849 { 0x00,
6846 1338, 6850 1339,
6847 NULL, 6851 NULL,
6848 NULL, 6852 NULL,
6849 }, 6853 },
6850 /* 71 */ 6854 /* 71 */
6851 { 0x66, 6855 { 0x66,
6852 NACL_OPCODE_NULL_OFFSET, 6856 NACL_OPCODE_NULL_OFFSET,
6853 g_OpcodeSeq + 72, 6857 g_OpcodeSeq + 72,
6854 NULL, 6858 NULL,
6855 }, 6859 },
6856 /* 72 */ 6860 /* 72 */
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
6896 NULL, 6900 NULL,
6897 }, 6901 },
6898 /* 79 */ 6902 /* 79 */
6899 { 0x00, 6903 { 0x00,
6900 NACL_OPCODE_NULL_OFFSET, 6904 NACL_OPCODE_NULL_OFFSET,
6901 g_OpcodeSeq + 80, 6905 g_OpcodeSeq + 80,
6902 NULL, 6906 NULL,
6903 }, 6907 },
6904 /* 80 */ 6908 /* 80 */
6905 { 0x00, 6909 { 0x00,
6906 1338, 6910 1339,
6907 NULL, 6911 NULL,
6908 NULL, 6912 NULL,
6909 }, 6913 },
6910 /* 81 */ 6914 /* 81 */
6911 { 0x66, 6915 { 0x66,
6912 NACL_OPCODE_NULL_OFFSET, 6916 NACL_OPCODE_NULL_OFFSET,
6913 g_OpcodeSeq + 82, 6917 g_OpcodeSeq + 82,
6914 NULL, 6918 NULL,
6915 }, 6919 },
6916 /* 82 */ 6920 /* 82 */
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
6956 NULL, 6960 NULL,
6957 }, 6961 },
6958 /* 89 */ 6962 /* 89 */
6959 { 0x00, 6963 { 0x00,
6960 NACL_OPCODE_NULL_OFFSET, 6964 NACL_OPCODE_NULL_OFFSET,
6961 g_OpcodeSeq + 90, 6965 g_OpcodeSeq + 90,
6962 NULL, 6966 NULL,
6963 }, 6967 },
6964 /* 90 */ 6968 /* 90 */
6965 { 0x00, 6969 { 0x00,
6966 1338, 6970 1339,
6967 NULL, 6971 NULL,
6968 NULL, 6972 NULL,
6969 }, 6973 },
6970 /* 91 */ 6974 /* 91 */
6971 { 0x90, 6975 { 0x90,
6972 1338, 6976 1339,
6973 NULL, 6977 NULL,
6974 NULL, 6978 NULL,
6975 }, 6979 },
6976 /* 92 */ 6980 /* 92 */
6977 { 0x90, 6981 { 0x90,
6978 1338, 6982 1339,
6979 NULL, 6983 NULL,
6980 g_OpcodeSeq + 93, 6984 g_OpcodeSeq + 93,
6981 }, 6985 },
6982 /* 93 */ 6986 /* 93 */
6983 { 0xf3, 6987 { 0xf3,
6984 NACL_OPCODE_NULL_OFFSET, 6988 NACL_OPCODE_NULL_OFFSET,
6985 g_OpcodeSeq + 94, 6989 g_OpcodeSeq + 94,
6986 NULL, 6990 NULL,
6987 }, 6991 },
6988 /* 94 */ 6992 /* 94 */
6989 { 0x90, 6993 { 0x90,
6990 1339, 6994 1340,
6991 NULL, 6995 NULL,
6992 NULL, 6996 NULL,
6993 }, 6997 },
6994 }; 6998 };
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